arm64: dts: qcom: sm8650: add OSM L3 node

Add the OSC L3 Cache controller node.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250211-topic-sm8650-ddr-bw-scaling-v2-1-a0c950540e68@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 86684cb9a9325618ddb74458621cf4bbdc1cc0d1..bc09e879c1440873a52daf3fc7a38f451f1f972c 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -5506,6 +5506,16 @@
                        };
                };
 
+               epss_l3: interconnect@17d90000 {
+                       compatible = "qcom,sm8650-epss-l3", "qcom,epss-l3";
+                       reg = <0 0x17d90000 0 0x1000>;
+
+                       clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
+                       clock-names = "xo", "alternate";
+
+                       #interconnect-cells = <1>;
+               };
+
                cpufreq_hw: cpufreq@17d91000 {
                        compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss";
                        reg = <0 0x17d91000 0 0x1000>,