arm64: dts: qcom: x1e80100: Wire up PCIe PHY NOCSR resets

Asserting the NOCSR reset line keeps the PHY registers in tact.
This allows us to avoid programming long tables of magic values in the
operating system.

Wire up these resets to PCIe PHY4 and 5 (it's there on the others).

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250203-topic-x1p4_dts-v2-4-72cd4cdc767b@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index b927a777270109959239ded6bcb5d0ab4bca42d8..62fa05210f68d6ddbbb0a34a36681e7addeaf58f 100644 (file)
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -3558,8 +3558,10 @@
                                      "pipe",
                                      "pipediv2";
 
-                       resets = <&gcc GCC_PCIE_5_PHY_BCR>;
-                       reset-names = "phy";
+                       resets = <&gcc GCC_PCIE_5_PHY_BCR>,
+                                <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>;
+                       reset-names = "phy",
+                                     "phy_nocsr";
 
                        assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>;
                        assigned-clock-rates = <100000000>;
@@ -3692,8 +3694,10 @@
                                      "pipe",
                                      "pipediv2";
 
-                       resets = <&gcc GCC_PCIE_4_PHY_BCR>;
-                       reset-names = "phy";
+                       resets = <&gcc GCC_PCIE_4_PHY_BCR>,
+                                <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>;
+                       reset-names = "phy",
+                                     "phy_nocsr";
 
                        assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
                        assigned-clock-rates = <100000000>;