]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
RISC-V: Fix another vf FP16 combine run test failures
authorPan Li <pan2.li@intel.com>
Fri, 25 Jul 2025 14:11:13 +0000 (22:11 +0800)
committerPan Li <pan2.li@intel.com>
Sun, 27 Jul 2025 03:12:34 +0000 (11:12 +0800)
Like Robin's fix for vf combine f16.c run tests, there is still
another failures similar.  This patch would like to fix it as
previous.

will commit it directly if the CI agrees.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c:
Add zvfh requirements and options.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c:
Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c

index 6be7d720603da953094e5d3f4db1716e8df9fee6..ddf49d5b2f23c5c0411f601d89b75e732164e5d1 100644 (file)
@@ -1,5 +1,9 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"
 
index dd28234b6e0ea0327bfda5a8080a619bc84eb4b4..a8749915569af8c8f540977ea6cb46e28576d20b 100644 (file)
@@ -1,5 +1,9 @@
 /* { dg-do run { target { riscv_v } } } */
-/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
 
 #include "vf_mulop.h"