This adds basic support for MediaTek MT8188 SoC.
Add watchdog support by adding upstream compatible string.
Add tphy support by adding "mediatek,generic-tphy-v2" compatible string
in arch/arm/dts/mt8188-u-boot.dtsi
Signed-off-by: Julien Masson <jmasson@baylibre.com>
Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
M: Igor Belwon <igor.belwon@mentallysanemainliners.org>
R: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
S: Maintained
+F: arch/arm/dts/mt*
F: arch/arm/mach-mediatek/
F: arch/arm/include/asm/arch-mediatek/
F: board/mediatek/
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2025 Baylibre SAS.
+ * Author: Julien Masson <jmasson@baylibre.com>
+ */
+
+&u3phy0 {
+ compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3",
+ "mediatek,generic-tphy-v2";
+};
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
+config TARGET_MT8188
+ bool "MediaTek MT8188 SoC"
+ select ARM64
+ help
+ The MediaTek MT8188 is a ARM64-based SoC with a dual-core Cortex-A78
+ cluster and a six-core Cortex-A55 cluster. It includes UART, SPI,
+ USB3.0 dual role, SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and
+ several LPDDR3 and LPDDR4 options.
+
config TARGET_MT8365
bool "MediaTek MT8365 SoC"
select ARM64
config MTK_BROM_HEADER_INFO
string
default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629
- default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
+ default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8188
default "lk=1" if TARGET_MT7623
config MTK_TZ_MOVABLE
obj-$(CONFIG_TARGET_MT7987) += mt7987/
obj-$(CONFIG_TARGET_MT7988) += mt7988/
obj-$(CONFIG_TARGET_MT8183) += mt8183/
+obj-$(CONFIG_TARGET_MT8188) += mt8188/
obj-$(CONFIG_TARGET_MT8365) += mt8365/
obj-$(CONFIG_TARGET_MT8512) += mt8512/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 MediaTek Inc.
+ * Copyright (C) 2025 BayLibre, SAS
+ * Author: Julien Masson <jmasson@baylibre.com>
+ * Chris-QJ Chen <chris-qj.chen@mediatek.com>
+ */
+
+#include <asm/global_data.h>
+#include <asm/system.h>
+#include <dm/uclass.h>
+#include <linux/sizes.h>
+#include <wdt.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+
+ fdtdec_setup_mem_size_base();
+
+ /*
+ * Limit gd->ram_top not exceeding SZ_4G. Some periphals like mmc
+ * requires DMA buffer allocated below SZ_4G.
+ *
+ * Note: SZ_1M is for adjusting gd->relocaddr, the reserved memory for
+ * u-boot itself.
+ */
+ if (gd->ram_base + gd->ram_size >= SZ_4G)
+ gd->mon_len = (gd->ram_base + gd->ram_size + SZ_1M) - SZ_4G;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = gd->ram_base;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
+int mtk_soc_early_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(void)
+{
+ struct udevice *wdt;
+
+ if (IS_ENABLED(CONFIG_PSCI_RESET)) {
+ psci_system_reset();
+ } else {
+ uclass_first_device(UCLASS_WDT, &wdt);
+ if (wdt)
+ wdt_expire_now(wdt, 0);
+ }
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: MediaTek MT8188\n");
+ return 0;
+}
{ .compatible = "mediatek,wdt"},
{ .compatible = "mediatek,mt6589-wdt"},
{ .compatible = "mediatek,mt7986-wdt" },
+ { .compatible = "mediatek,mt8188-wdt" },
{}
};