drm/amd: Allow printing VanGogh OD SCLK levels without setting dpm to manual

[ Upstream commit 2d1ec1e955414e8e8358178011c35afca1a1c0b1 ]

Several other ASICs allow printing OD SCLK levels without setting DPM
control to manual.  When OD is disabled it will show the range the
hardware supports. When OD is enabled it will show what values have
been programmed. Adjust VanGogh to work the same.

Cc: Pierre-Loup A. Griffais <pgriffais@valvesoftware.com>
Reported-by: Vicki Pfau <vi@endrift.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Link: https://lore.kernel.org/r/20250609031227.479079-1-superm1@kernel.org
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 454216bd6f1dd2df1ac1187fe655d96d1eebf5e3..4fabecaa2b4195e5558f2b4f45c9da3df61e58f6 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -686,7 +686,6 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
 {
        DpmClocks_t *clk_table = smu->smu_table.clocks_table;
        SmuMetrics_t metrics;
-       struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
        int i, idx, size = 0, ret = 0;
        uint32_t cur_value = 0, value = 0, count = 0;
        bool cur_value_match_level = false;
@@ -702,31 +701,25 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
 
        switch (clk_type) {
        case SMU_OD_SCLK:
-               if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
-                       size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
-                       size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
-                       (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
-                       size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
-                       (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
-               }
+               size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
+               size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
+               (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
+               size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
+               (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
                break;
        case SMU_OD_CCLK:
-               if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
-                       size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n",  smu->cpu_core_id_select);
-                       size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
-                       (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
-                       size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
-                       (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
-               }
+               size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n",  smu->cpu_core_id_select);
+               size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
+               (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
+               size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
+               (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
                break;
        case SMU_OD_RANGE:
-               if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
-                       size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
-                       size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
-                               smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
-                       size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
-                               smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
-               }
+               size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
+               size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
+                       smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
+               size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
+                       smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
                break;
        case SMU_SOCCLK:
                /* the level 3 ~ 6 of socclk use the same frequency for vangogh */