perf/x86/msr: Add Airmont NP

Like Airmont, the Airmont NP (aka Intel / MaxLinear Lightning Mountain)
supports SMI_COUNT MSR.

Signed-off-by: Martin Schiller <ms@dev.tdt.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Link: https://patch.msgid.link/20251124074846.9653-2-ms@dev.tdt.de

diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 7f5007a4752a1738f4671fed6c90c077a7e62ecd..8052596b8503644aa85c733e25341004ccf320c4 100644 (file)
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -78,6 +78,7 @@ static bool test_intel(int idx, void *data)
        case INTEL_ATOM_SILVERMONT:
        case INTEL_ATOM_SILVERMONT_D:
        case INTEL_ATOM_AIRMONT:
+       case INTEL_ATOM_AIRMONT_NP:
 
        case INTEL_ATOM_GOLDMONT:
        case INTEL_ATOM_GOLDMONT_D: