dt-bindings: clock: qcom: document the Milos Display Clock Controller

Add bindings documentation for the Milos (e.g. SM7635) Display Clock
Controller.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-6-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/Documentation/devicetree/bindings/clock/qcom,milos-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,milos-dispcc.yaml
new file mode 100644 (file)
index 0000000..9490880
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,milos-dispcc.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,milos-dispcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller on Milos
+
+maintainers:
+  - Luca Weiss <luca.weiss@fairphone.com>
+
+description: |
+  Qualcomm display clock control module provides the clocks, resets and power
+  domains on Milos.
+
+  See also: include/dt-bindings/clock/qcom,milos-dispcc.h
+
+properties:
+  compatible:
+    const: qcom,milos-dispcc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Sleep clock source
+      - description: Display's AHB clock
+      - description: GPLL0 source from GCC
+      - description: Byte clock from DSI PHY0
+      - description: Pixel clock from DSI PHY0
+      - description: Link clock from DP PHY0
+      - description: VCO DIV clock from DP PHY0
+
+required:
+  - compatible
+  - clocks
+  - '#power-domain-cells'
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,milos-gcc.h>
+    #include <dt-bindings/phy/phy-qcom-qmp.h>
+    clock-controller@af00000 {
+        compatible = "qcom,milos-dispcc";
+        reg = <0x0af00000 0x20000>;
+        clocks = <&bi_tcxo_div2>,
+                 <&sleep_clk>,
+                 <&gcc GCC_DISP_AHB_CLK>,
+                 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
+                 <&mdss_dsi0_phy 0>,
+                 <&mdss_dsi0_phy 1>,
+                 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+                 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+        #clock-cells = <1>;
+        #reset-cells = <1>;
+        #power-domain-cells = <1>;
+    };
+
+...

diff --git a/include/dt-bindings/clock/qcom,milos-dispcc.h b/include/dt-bindings/clock/qcom,milos-dispcc.h
new file mode 100644 (file)
index 0000000..c70f23f
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,milos-dispcc.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_MILOS_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_MILOS_H
+
+/* DISP_CC clocks */
+#define DISP_CC_PLL0                                           0
+#define DISP_CC_MDSS_ACCU_CLK                                  1
+#define DISP_CC_MDSS_AHB1_CLK                                  2
+#define DISP_CC_MDSS_AHB_CLK                                   3
+#define DISP_CC_MDSS_AHB_CLK_SRC                               4
+#define DISP_CC_MDSS_BYTE0_CLK                                 5
+#define DISP_CC_MDSS_BYTE0_CLK_SRC                             6
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC                         7
+#define DISP_CC_MDSS_BYTE0_INTF_CLK                            8
+#define DISP_CC_MDSS_DPTX0_AUX_CLK                             9
+#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC                         10
+#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK                          11
+#define DISP_CC_MDSS_DPTX0_LINK_CLK                            12
+#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC                                13
+#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC                    14
+#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK                       15
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK                          16
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC                      17
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK                          18
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC                      19
+#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK            20
+#define DISP_CC_MDSS_ESC0_CLK                                  21
+#define DISP_CC_MDSS_ESC0_CLK_SRC                              22
+#define DISP_CC_MDSS_MDP1_CLK                                  23
+#define DISP_CC_MDSS_MDP_CLK                                   24
+#define DISP_CC_MDSS_MDP_CLK_SRC                               25
+#define DISP_CC_MDSS_MDP_LUT1_CLK                              26
+#define DISP_CC_MDSS_MDP_LUT_CLK                               27
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK                          28
+#define DISP_CC_MDSS_PCLK0_CLK                                 29
+#define DISP_CC_MDSS_PCLK0_CLK_SRC                             30
+#define DISP_CC_MDSS_RSCC_AHB_CLK                              31
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK                            32
+#define DISP_CC_MDSS_VSYNC1_CLK                                        33
+#define DISP_CC_MDSS_VSYNC_CLK                                 34
+#define DISP_CC_MDSS_VSYNC_CLK_SRC                             35
+#define DISP_CC_SLEEP_CLK                                      36
+#define DISP_CC_SLEEP_CLK_SRC                                  37
+#define DISP_CC_XO_CLK                                         38
+#define DISP_CC_XO_CLK_SRC                                     39
+
+/* DISP_CC resets */
+#define DISP_CC_MDSS_CORE_BCR                                  0
+#define DISP_CC_MDSS_CORE_INT2_BCR                             1
+#define DISP_CC_MDSS_RSCC_BCR                                  2
+
+/* DISP_CC power domains */
+#define DISP_CC_MDSS_CORE_GDSC                                 0
+#define DISP_CC_MDSS_CORE_INT2_GDSC                            1
+
+#endif