Merge branch 'for-7.0/cxl-prm-translation' into cxl-for-next

Add support for normalized CXL address translation through ACPI PRM method
to support AMD Zen5 platforms. Including a conventions doc that explains
how the translation is implemented and for future implementations that
need such setup to comply with the current implementation method.

cxl: Disable HPA/SPA translation handlers for Normalized Addressing
cxl/region: Factor out code into cxl_region_setup_poison()
cxl/atl: Lock decoders that need address translation
cxl: Enable AMD Zen5 address translation using ACPI PRMT
cxl/acpi: Prepare use of EFI runtime services
cxl: Introduce callback for HPA address ranges translation
cxl/region: Use region data to get the root decoder
cxl/region: Add @hpa_range argument to function cxl_calc_interleave_pos()
cxl/region: Separate region parameter setup and region construction
cxl: Simplify cxl_root_ops allocation and handling
cxl/region: Store HPA range in struct cxl_region
cxl/region: Store root decoder in struct cxl_region
cxl/region: Rename misleading variable name @hpa to @hpa_range
Documentation/driver-api/cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement
cxl, doc: Moving conventions in separate files
cxl, doc: Remove isonum.txt inclusion

diff --cc drivers/cxl/Kconfig
index 5b5aa941ad2fb2b127ea29494bf034cf7d3dfc54,103950a9b73e8eba5eeb615d52d480be1b835ff9..4589bf11d3fe00f89062c5bda4838603ac77eb14
--- 1/drivers/cxl/Kconfig
--- 2/drivers/cxl/Kconfig
+++ b/drivers/cxl/Kconfig
@@@ -233,8 -233,9 +233,13 @@@ config CXL_MC
        def_bool y
        depends on X86_MCE && MEMORY_FAILURE
  
 +config CXL_RAS
 +      def_bool y
 +      depends on ACPI_APEI_GHES && PCIEAER && CXL_BUS
 +
+ config CXL_ATL
+       def_bool y
+       depends on CXL_REGION
+       depends on ACPI_PRMT && AMD_NB
+ 
  endif

diff --cc drivers/cxl/acpi.c
Simple merge

diff --cc drivers/cxl/core/Makefile
index b37f38d502d8c344fa6b412c4973d22242b76ce0,11fe272a6e29cd1e41d9b2f6e14eb3d24505178b..a639a949997202fb795d0d9c6da0ef0b06ec96ee
--- 1/drivers/cxl/core/Makefile
--- 2/drivers/cxl/core/Makefile
+++ b/drivers/cxl/core/Makefile
@@@ -19,5 -20,4 +19,6 @@@ cxl_core-$(CONFIG_CXL_REGION) += region
  cxl_core-$(CONFIG_CXL_MCE) += mce.o
  cxl_core-$(CONFIG_CXL_FEATURES) += features.o
  cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) += edac.o
 +cxl_core-$(CONFIG_CXL_RAS) += ras.o
 +cxl_core-$(CONFIG_CXL_RAS) += ras_rch.o
+ cxl_core-$(CONFIG_CXL_ATL) += atl.o

diff --cc drivers/cxl/core/core.h
Simple merge

diff --cc drivers/cxl/core/port.c
Simple merge

diff --cc drivers/cxl/core/region.c
index 96888d87a8df298301c6f8e42a7d7c9cde9b9260,8e92b491d686dd982b46f98870b79e806f2780d8..bd4c4a4a27daa220eea0a0fabf0c668cf8b87bf2
--- 1/drivers/cxl/core/region.c
--- 2/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@@ -3246,8 -3126,7 +3257,8 @@@ static bool region_is_unaligned_mod3(st
  u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd,
                   u64 dpa)
  {
-       struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent);
+       struct cxl_root_decoder *cxlrd = cxlr->cxlrd;
 +      struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
        struct cxl_region_params *p = &cxlr->params;
        struct cxl_endpoint_decoder *cxled = NULL;
        u64 dpa_offset, hpa_offset, hpa;

diff --cc drivers/cxl/cxl.h
index 478d8803b464727b9a5a459bda48ed6cdae8c840,de30a87600be1aaae504ccb02e86c08af5346fc8..04c673e7cdb0b30d2ce98b71e1d1e6b3e6fa0a86
--- 1/drivers/cxl/cxl.h
--- 2/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@@ -780,10 -792,7 +794,9 @@@ struct cxl_port *devm_cxl_add_port(stru
                                   struct device *uport_dev,
                                   resource_size_t component_reg_phys,
                                   struct cxl_dport *parent_dport);
- struct cxl_root *devm_cxl_add_root(struct device *host,
-                                  const struct cxl_root_ops *ops);
+ struct cxl_root *devm_cxl_add_root(struct device *host);
 +int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
 +                        struct cxl_dport *parent_dport);
  struct cxl_root *find_cxl_root(struct cxl_port *port);
  
  DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_device(&_T->port.dev))
@@@ -807,6 -816,21 +820,13 @@@ struct cxl_dport *devm_cxl_add_rch_dpor
                                         struct device *dport_dev, int port_id,
                                         resource_size_t rcrb);
  
 -#ifdef CONFIG_PCIEAER_CXL
 -void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport);
 -void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host);
 -#else
 -static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport,
 -                                              struct device *host) { }
 -#endif
 -
+ #ifdef CONFIG_CXL_ATL
+ void cxl_setup_prm_address_translation(struct cxl_root *cxl_root);
+ #else
+ static inline
+ void cxl_setup_prm_address_translation(struct cxl_root *cxl_root) {}
+ #endif
+ 
  struct cxl_decoder *to_cxl_decoder(struct device *dev);
  struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev);
  struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev);

diff --cc tools/testing/cxl/Kbuild
index 982e8ea28b92443b74356b099e208b8525767921,612d8edbfc6fec5551aa6c37204d301843f1c06b..53d84a6874b76b0371d599069c2d2ab32f2553fd
--- 1/tools/testing/cxl/Kbuild
--- 2/tools/testing/cxl/Kbuild
+++ b/tools/testing/cxl/Kbuild
@@@ -63,8 -63,7 +63,9 @@@ cxl_core-$(CONFIG_CXL_REGION) += $(CXL_
  cxl_core-$(CONFIG_CXL_MCE) += $(CXL_CORE_SRC)/mce.o
  cxl_core-$(CONFIG_CXL_FEATURES) += $(CXL_CORE_SRC)/features.o
  cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) += $(CXL_CORE_SRC)/edac.o
 +cxl_core-$(CONFIG_CXL_RAS) += $(CXL_CORE_SRC)/ras.o
 +cxl_core-$(CONFIG_CXL_RAS) += $(CXL_CORE_SRC)/ras_rch.o
+ cxl_core-$(CONFIG_CXL_ATL) += $(CXL_CORE_SRC)/atl.o
  cxl_core-y += config_check.o
  cxl_core-y += cxl_core_test.o
  cxl_core-y += cxl_core_exports.o