S/390: z13 Change predicates of 128 bit add sub.

So far usage of 128 bit add/sub instruction was rejected if the second
operand was a constant because the predicate rejected this.

gcc/testsuite/ChangeLog:

	* gcc.target/s390/vector/int128-1.c: New test.

gcc/ChangeLog:

	* config/s390/vector.md ("<ti*>add<mode>3", "<ti*>sub<mode>3"):
	Change the predicate of op2 from nonimmediate to general and let
	reload fix it if necessary.

From-SVN: r233554

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 06fedf0dd464b2e46cd3472476e140304dce00fc..471a01bc5dd1c4294e655f855075d0c1ecde43b7 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2016-02-19  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
+
+       * config/s390/vector.md ("<ti*>add<mode>3", "<ti*>sub<mode>3"):
+       Change the predicate of op2 from nonimmediate to general and let
+       reload fix it if necessary.
+
 2016-02-19  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 
        * config/s390/vecintrin.h (vec_sub_u128): Define missing macro.

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 2302a8f4bd631dc308c85fbbf4cbe37e6fb158f8..cdb9ba61a73be5875fe9525914c79aeceb6f9e32 100644 (file)
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -454,7 +454,7 @@
 (define_insn "<ti*>add<mode>3"
   [(set (match_operand:VIT           0 "nonimmediate_operand" "=v")
        (plus:VIT (match_operand:VIT 1 "nonimmediate_operand"  "v")
-                 (match_operand:VIT 2 "nonimmediate_operand"  "v")))]
+                 (match_operand:VIT 2 "general_operand"  "v")))]
   "TARGET_VX"
   "va<bhfgq>\t%v0,%v1,%v2"
   [(set_attr "op_type" "VRR")])
@@ -463,7 +463,7 @@
 (define_insn "<ti*>sub<mode>3"
   [(set (match_operand:VIT            0 "nonimmediate_operand" "=v")
        (minus:VIT (match_operand:VIT 1 "nonimmediate_operand"  "v")
-                  (match_operand:VIT 2 "nonimmediate_operand"  "v")))]
+                  (match_operand:VIT 2 "general_operand"  "v")))]
   "TARGET_VX"
   "vs<bhfgq>\t%v0,%v1,%v2"
   [(set_attr "op_type" "VRR")])

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index abb2ed6ad3e96c8beb2eb8d0877c9a8f70b44423..4a0dbabb3b711677c4a0de8eb7ba96f930c1cb7b 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2016-02-19  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
+
+       * gcc.target/s390/vector/int128-1.c: New test.
+
 2016-02-19  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 
        * gcc.target/s390/vector/vec-vcond-1.c: New test.

diff --git a/gcc/testsuite/gcc.target/s390/vector/int128-1.c b/gcc/testsuite/gcc.target/s390/vector/int128-1.c
new file mode 100644 (file)
index 0000000..b4a16b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/int128-1.c
@@ -0,0 +1,47 @@
+/* Check that vaq/vsq are used for int128 operations.  */
+
+/* { dg-do compile { target { lp64 } } } */
+/* { dg-options "-O3 -mzarch -march=z13" } */
+
+
+const __int128 c = (__int128)0x0123456789abcd55 + ((__int128)7 << 64);
+
+
+__int128
+addreg(__int128 a, __int128 b)
+{
+  return a + b;
+}
+
+__int128
+addconst(__int128 a)
+{
+  return a + c;
+}
+
+__int128
+addmem(__int128 *a, __int128_t *b)
+{
+  return *a + *b;
+}
+
+__int128
+subreg(__int128 a, __int128 b)
+{
+  return a - b;
+}
+
+__int128
+subconst(__int128 a)
+{
+  return a - c; /* This becomes vaq as well.  */
+}
+
+__int128
+submem(__int128 *a, __int128_t *b)
+{
+  return *a - *b;
+}
+
+/* { dg-final { scan-assembler-times "vaq" 4 } } */
+/* { dg-final { scan-assembler-times "vsq" 2 } } */