Document the Last Level Cache Controller on Eliza SoC. Eliza LLCC has 2
base register regions and an additional AND, OR broadcast region, total 4
register regions.
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260513-eliza-llcc-v2-1-27381ae833d5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
properties:
compatible:
enum:
+ - qcom,eliza-llcc
- qcom,glymur-llcc
- qcom,hawi-llcc
- qcom,ipq5424-llcc
properties:
memory-region: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,eliza-llcc
+ then:
+ properties:
+ reg:
+ items:
+ - description: LLCC0 base register region
+ - description: LLCC2 base register region
+ - description: LLCC broadcast OR register region
+ - description: LLCC broadcast AND register region
+ reg-names:
+ items:
+ - const: llcc0_base
+ - const: llcc2_base
+ - const: llcc_broadcast_base
+ - const: llcc_broadcast_and_base
+
additionalProperties: false
examples: