drm/msm/adreno: Expose a PARAM to check AQE support

AQE (Applicaton Qrisc Engine) is required to support VK ray-pipeline. Two
conditions should be met to use this HW:
  1. AQE firmware should be loaded and programmed
  2. Preemption support

Expose a new MSM_PARAM to allow userspace to query its support.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714685/
Message-ID: <20260327-a8xx-gpu-batch2-v2-17-2b53c38d2101@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index ae592022bebcd7e2bd78e779df77ad782823ccdb..615509c8917e81b1bac9dfba518b8df9bd98f58e 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2604,6 +2604,17 @@ static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu,
        return 0;
 }
 
+static bool a6xx_aqe_is_enabled(struct adreno_gpu *adreno_gpu)
+{
+       struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
+
+       /*
+        * AQE uses preemption context record as scratch pad, so check if
+        * preemption is enabled
+        */
+       return (adreno_gpu->base.nr_rings > 1) && !!a6xx_gpu->aqe_bo;
+}
+
 static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
 {
        struct msm_drm_private *priv = dev->dev_private;
@@ -2803,6 +2814,7 @@ const struct adreno_gpu_funcs a7xx_gpu_funcs = {
        .bus_halt = a6xx_bus_clear_pending_transactions,
        .mmu_fault_handler = a6xx_fault_handler,
        .gx_is_on = a7xx_gmu_gx_is_on,
+       .aqe_is_enabled = a6xx_aqe_is_enabled,
 };
 
 const struct adreno_gpu_funcs a8xx_gpu_funcs = {
@@ -2831,4 +2843,5 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs = {
        .bus_halt = a8xx_bus_clear_pending_transactions,
        .mmu_fault_handler = a8xx_fault_handler,
        .gx_is_on = a8xx_gmu_gx_is_on,
+       .aqe_is_enabled = a6xx_aqe_is_enabled,
 };

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 0dbeb332f8d1d0b8887bd2a99422553d04e99586..85d135a9d336c37d49cb1dc6188d27c1c10f4f00 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -441,6 +441,10 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx,
        case MSM_PARAM_HAS_PRR:
                *value = adreno_smmu_has_prr(gpu);
                return 0;
+       case MSM_PARAM_AQE:
+               *value = !!(adreno_gpu->funcs->aqe_is_enabled &&
+                           adreno_gpu->funcs->aqe_is_enabled(adreno_gpu));
+               return 0;
        default:
                return UERR(EINVAL, drm, "%s: invalid param: %u", gpu->name, param);
        }

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 834f6fd2a89eaefa4689541bc35963b8f08ea36f..ec643b84646be6076ddddf938534bec1e87ee7fd 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -80,6 +80,7 @@ struct adreno_gpu_funcs {
        void (*bus_halt)(struct adreno_gpu *adreno_gpu, bool gx_off);
        int (*mmu_fault_handler)(void *arg, unsigned long iova, int flags, void *data);
        bool (*gx_is_on)(struct adreno_gpu *adreno_gpu);
+       bool (*aqe_is_enabled)(struct adreno_gpu *adreno_gpu);
 };
 
 struct adreno_reglist {

diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index 5c67294edc953b386bdb1f9af7388b321b2d8388..b99098792371e6e681de3e9224c1b475f6d77ec3 100644 (file)
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -117,6 +117,7 @@ struct drm_msm_timespec {
  * ioctl will throw -EPIPE.
  */
 #define MSM_PARAM_EN_VM_BIND 0x16  /* WO, once */
+#define MSM_PARAM_AQE       0x17  /* RO */
 
 /* For backwards compat.  The original support for preemption was based on
  * a single ring per priority level so # of priority levels equals the #