Merge branch 'clk-fixes' into clk-next

Resolve conflicts with i.MX95 changes 88768d6f8c13 ("clk:
imx95-blk-ctl: Rename lvds and displaymix csr blk") in clk-imx
and aacc875a448d ("clk: imx: Fix an out-of-bounds access in
dispmix_csr_clk_dev_data") in clk-fixes.

* clk-fixes:
  clk: sunxi-ng: v3s: Fix TCON clock parents
  clk: sunxi-ng: v3s: Fix CSI1 MCLK clock name
  clk: sunxi-ng: v3s: Fix CSI SCLK clock name
  dt-bindings: clock: mediatek: Add #reset-cells property for MT8188
  clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data
  clk: scmi: Handle case where child clocks are initialized before their parents
  clk: sunxi-ng: a523: Mark MBUS clock as critical

diff --cc drivers/clk/clk-scmi.c
Simple merge

diff --cc drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index 0c01aca4e19bf484193968d4359b84b13a9e43ad,52e4369664c587b55d0e70b1c1d415850faff610..05595ac51b76af788753c1b4c1a8c452115b9404
--- 1/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
--- 2/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@@ -347,13 -347,12 +347,13 @@@ static SUNXI_CCU_GATE(dram_ohci_clk,    "d
  
  static const char * const de_parents[] = { "pll-video", "pll-periph0" };
  static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
 -                               0x104, 0, 4, 24, 2, BIT(31),
 -                               CLK_SET_RATE_PARENT);
 +                               0x104, 0, 4, 24, 3, BIT(31),
 +                               CLK_SET_RATE_NO_REPARENT);
  
- static const char * const tcon_parents[] = { "pll-video" };
+ static const char * const tcon_parents[] = { "pll-video", "pll-periph0" };
  static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
 -                               0x118, 0, 4, 24, 3, BIT(31), 0);
 +                               0x118, 0, 4, 24, 3, BIT(31),
 +                               CLK_SET_RATE_NO_REPARENT);
  
  static SUNXI_CCU_GATE(csi_misc_clk,   "csi-misc",     "osc24M",
                      0x130, BIT(31), 0);