re PR target/48366 (ICE in extract_constrain_insn_cached, at recog.c:2024)

	* config/pa/pa.h (REGISTER_MOVE_COST): Increase to 18 cost of
	move from floating point to shift amount register.

	Backport from mainline:
	2011-04-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	PR target/48366
	* config/pa/pa.c (emit_move_sequence): Remove secondary reload
	support for floating point to shift amount amount register copies.
	(pa_secondary_reload): Return GENERAL_REGS for floating point/shift
	amount register copies.
	* config/pa/pa32-regs.h (HARD_REGNO_MODE_OK): For shift amount
	register, return false if mode isn't a scalar integer mode.
	* config/pa/pa64-regs.h (HARD_REGNO_MODE_OK): Likewise.

From-SVN: r172710

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ffd529c8d649eccb9c3ab4cc29c1ed38fe557c88..f980537d577d05843e9840efc8f2de622cff40e1 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,20 @@
+2011-04-19  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+       * config/pa/pa.h (REGISTER_MOVE_COST): Increase to 18 cost of
+       move from floating point to shift amount register.
+
+       Backport from mainline:
+       2011-04-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+       PR target/48366
+       * config/pa/pa.c (emit_move_sequence): Remove secondary reload
+       support for floating point to shift amount amount register copies.
+       (pa_secondary_reload): Return GENERAL_REGS for floating point/shift
+       amount register copies.
+       * config/pa/pa32-regs.h (HARD_REGNO_MODE_OK): For shift amount
+       register, return false if mode isn't a scalar integer mode.
+       * config/pa/pa64-regs.h (HARD_REGNO_MODE_OK): Likewise.
+
 2011-04-16  Jakub Jelinek  <jakub@redhat.com>
 
        Backported from 4.6 branch

diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index 801b01e45613372fe569600ae7a1fa8bceb30e72..6318611bd9af9347a15efd253a6052c71b3261f3 100644 (file)
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -1618,15 +1618,12 @@ emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
       return 1;
     }
   /* Handle secondary reloads for SAR.  These occur when trying to load
-     the SAR from memory, FP register, or with a constant.  */
+     the SAR from memory or a constant.  */
   else if (scratch_reg
           && GET_CODE (operand0) == REG
           && REGNO (operand0) < FIRST_PSEUDO_REGISTER
           && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
-          && (GET_CODE (operand1) == MEM
-              || GET_CODE (operand1) == CONST_INT
-              || (GET_CODE (operand1) == REG
-                  && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
+          && (GET_CODE (operand1) == MEM || GET_CODE (operand1) == CONST_INT))
     {
       /* D might not fit in 14 bits either; for such cases load D into
         scratch reg.  */
@@ -5695,6 +5692,10 @@ output_arg_descriptor (rtx call_insn)
   fputc ('\n', asm_out_file);
 }
 \f
+/* Inform reload about cases where moving X with a mode MODE to a register in
+   RCLASS requires an extra scratch or immediate register.  Return the class
+   needed for the immediate register.  */
+
 static enum reg_class
 pa_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
                     enum machine_mode mode, secondary_reload_info *sri)
@@ -5794,20 +5795,27 @@ pa_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
       return NO_REGS;
     }
 
-  /* We need a secondary register (GPR) for copies between the SAR
-     and anything other than a general register.  */
-  if (rclass == SHIFT_REGS && (regno <= 0 || regno >= 32))
+  /* A SAR<->FP register copy requires an intermediate general register
+     and secondary memory.  We need a secondary reload with a general
+     scratch register for spills.  */
+  if (rclass == SHIFT_REGS)
     {
-      sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode];
-      return NO_REGS;
+      /* Handle spill.  */
+      if (regno >= FIRST_PSEUDO_REGISTER || regno < 0)
+       {
+         sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode];
+         return NO_REGS;
+       }
+
+      /* Handle FP copy.  */
+      if (FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))
+       return GENERAL_REGS;
     }
 
-  /* A SAR<->FP register copy requires a secondary register (GPR) as
-     well as secondary memory.  */
   if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
-      && (REGNO_REG_CLASS (regno) == SHIFT_REGS
-      && FP_REG_CLASS_P (rclass)))
-    sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode];
+      && REGNO_REG_CLASS (regno) == SHIFT_REGS
+      && FP_REG_CLASS_P (rclass))
+    return GENERAL_REGS;
 
   return NO_REGS;
 }

diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index ab4c7f99edc8db952647f4d9c949a8f238c3216d..aec5fa12d4a492a40a3cb00de097cc8ee8c5997e 100644 (file)
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -1564,6 +1564,7 @@ do {                                                                      \
    Other copies are reasonably cheap.  */
 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
  (CLASS1 == SHIFT_REGS ? 0x100                                 \
+  : CLASS2 == SHIFT_REGS && FP_REG_CLASS_P (CLASS1) ? 18       \
   : FP_REG_CLASS_P (CLASS1) && ! FP_REG_CLASS_P (CLASS2) ? 16  \
   : FP_REG_CLASS_P (CLASS2) && ! FP_REG_CLASS_P (CLASS1) ? 16  \
   : 2)

diff --git a/gcc/config/pa/pa32-regs.h b/gcc/config/pa/pa32-regs.h
index 4463c631d38a2e05438210fa51a674e78f485ebc..43b48221a0234ab8cbce035e132eda259564d164 100644 (file)
--- a/gcc/config/pa/pa32-regs.h
+++ b/gcc/config/pa/pa32-regs.h
@@ -202,6 +202,7 @@
    registers.  */
 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
   ((REGNO) == 0 ? (MODE) == CCmode || (MODE) == CCFPmode               \
+   : (REGNO) == 88 ? SCALAR_INT_MODE_P (MODE)                          \
    : !TARGET_PA_11 && FP_REGNO_P (REGNO)                               \
      ? (VALID_FP_MODE_P (MODE)                                         \
        && (GET_MODE_SIZE (MODE) <= 8                                   \

diff --git a/gcc/config/pa/pa64-regs.h b/gcc/config/pa/pa64-regs.h
index 042e0c47c68ff0ece6aabfd95b7fc4472c6dfe1f..b2a9432c4012ee0de026a1a96ac3d1e8aba0649c 100644 (file)
--- a/gcc/config/pa/pa64-regs.h
+++ b/gcc/config/pa/pa64-regs.h
@@ -161,10 +161,11 @@ along with GCC; see the file COPYING3.  If not see
 
 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
    On the HP-PA, the cpu registers can hold any mode.  We
-   force this to be an even register is it cannot hold the full mode.  */
+   force this to be an even register if it cannot hold the full mode.  */
 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
   ((REGNO) == 0                                                                \
    ? (MODE) == CCmode || (MODE) == CCFPmode                            \
+   : (REGNO) == 60 ? SCALAR_INT_MODE_P (MODE)                          \
    /* Make wide modes be in aligned registers.  */                     \
    : FP_REGNO_P (REGNO)                                                        \
      ? (VALID_FP_MODE_P (MODE)                                         \