Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 53926550eb4703d2c691a2f3e30c7fb05ffae978..81ec0707999ea1ccb0e1f238b2c71278872f1203 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,72 @@
+2025-08-22  Kishan Parmar  <kishan@linux.ibm.com>
+
+       PR target/118890
+       * config/rs6000/rs6000.cc (can_be_rotated_to_negative_lis): Add bounds
+       checks for shift counts to prevent undefined behavior.
+       (rs6000_emit_set_long_const): Likewise.
+
+2025-08-22  Jeff Law  <jlaw@ventanamicro.com>
+
+       PR rtl-optimization/120553
+       * ifcvt.cc (noce_try_sign_bit_splat): New function.
+       (noce_process_if_block): Use it.
+
+2025-08-22  Richard Biener  <rguenther@suse.de>
+
+       * tree-vect-loop.cc (vectorizable_live_operation): Pass
+       the representative of the PHIs node to
+       vect_create_epilog_for_reduction.
+
+2025-08-22  Richard Biener  <rguenther@suse.de>
+
+       * tree-vect-loop.cc (vectorizable_lane_reducing): Get
+       reduction info properly.  Adjust checks according to
+       comments.
+       (vectorizable_reduction): Do not set STMT_VINFO_REDUC_VECTYPE_IN
+       on the reduc info.
+       (vect_transform_reduction): Query STMT_VINFO_REDUC_VECTYPE_IN
+       on the actual reduction stmt, not the info.
+
+2025-08-22  Pan Li  <pan2.li@intel.com>
+
+       * match.pd: Add form 3 for unsigned SAT_MUL.
+
+2025-08-22  H.J. Lu  <hjl.tools@gmail.com>
+
+       PR target/121635
+       * config/i386/i386-features.cc (ix86_emit_tls_call): Emit the
+       TLS call after NOTE_INSN_FUNCTION_BEG.
+
+2025-08-22  Richard Biener  <rguenther@suse.de>
+
+       * tree-vect-loop.cc (get_initial_defs_for_reduction): Adjust
+       comment.
+       (vect_create_epilog_for_reduction): Get at the reduction
+       kind via the instance, re-use the slp_reduc flag instead
+       of checking REDUC_GROUP_FIRST_ELEMENT again.
+       Remove unreachable code.
+       (vectorizable_reduction): Compute a reduc_chain flag from
+       the SLP instance kind, avoid REDUC_GROUP_FIRST_ELEMENT
+       checks.
+       (vect_transform_cycle_phi): Likewise.
+       (vectorizable_live_operation): Check the SLP instance
+       kind instead of REDUC_GROUP_FIRST_ELEMENT.
+
+2025-08-22  Richard Biener  <rguenther@suse.de>
+
+       * tree-parloops.cc (parloops_is_simple_reduction): Pass
+       in double reduction inner loop LC phis and query that.
+       (parloops_force_simple_reduction): Similar, but set it.
+       Check for valid reduction types here.
+       (valid_reduction_p): Remove.
+       (gather_scalar_reductions): Adjust, fixup double
+       reduction inner loop processing.
+
+2025-08-22  Sebastian Huber  <sebastian.huber@embedded-brains.de>
+
+       * config/riscv/t-rtems: Add -mstrict-align multilibs for
+       targets without support for misaligned access in hardware.
+
 2025-08-21  Dimitar Dimitrov  <dimitar@dinux.eu>
 
        * config/pru/pru.cc (pru_init_libfuncs): Set softmpy libgcc

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 7d0185db72cc7042b32a57fd652abd5d3d580f18..edde633f906164e1d655fa0482bdddab5425f528 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20250822
+20250823

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index edd964025ede8d2d133d5dd1a848ddee9d646436..b28c22186166d6624d40adf846d2060ac3c27b35 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,63 @@
+2025-08-22  Jeff Law  <jlaw@ventanamicro.com>
+
+       PR rtl-optimization/120553
+       * gcc.target/riscv/pr120553-1.c: New test.
+       * gcc.target/riscv/pr120553-2.c: New test.
+       * gcc.target/riscv/pr120553-3.c: New test.
+       * gcc.target/riscv/pr120553-4.c: New test.
+       * gcc.target/riscv/pr120553-5.c: New test.
+       * gcc.target/riscv/pr120553-6.c: New test.
+       * gcc.target/riscv/pr120553-7.c: New test.
+       * gcc.target/riscv/pr120553-8.c: New test.
+
+2025-08-22  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/sat/sat_arith.h: Add test helper macros.
+       * gcc.target/riscv/sat/sat_u_mul-4-u16-from-u128.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-4-u16-from-u32.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-4-u16-from-u64.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-4-u16-from-u64.rv32.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-4-u32-from-u128.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-4-u32-from-u64.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-4-u32-from-u64.rv32.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-4-u64-from-u128.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-4-u8-from-u128.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-4-u8-from-u16.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-4-u8-from-u32.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-4-u8-from-u64.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-4-u8-from-u64.rv32.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u128.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u32.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u64.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u64.rv32.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u128.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u64.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u64.rv32.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-run-4-u64-from-u128.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u128.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u16.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u32.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u64.c: New test.
+       * gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u64.rv32.c: New test.
+
+2025-08-22  H.J. Lu  <hjl.tools@gmail.com>
+
+       PR target/121635
+       * gcc.target/i386/pr121635-1a.c: New test.
+       * gcc.target/i386/pr121635-1b.c: Likewise.
+
+2025-08-22  Nathaniel Shead  <nathanieloshead@gmail.com>
+
+       * g++.dg/abi/mangle83.C: Disable implicit enum test for
+       -fshort-enums.
+
+2025-08-22  Alexandre Oliva  <oliva@adacore.com>
+
+       PR rtl-optimization/120424
+       * lib/target-supports.exp (arm arches): Add arm_arch_v7.
+       * g++.target/arm/pr120424.C: Require armv7 support.  Use
+       dg-add-options arm_arch_v7 instead of explicit -march=armv7.
+
 2025-08-21  Steven G. Kargl  <kargl@gcc.gnu.org>
 
        PR fortran/121627