arm64: dts: renesas: ebisu: Describe PCIe/USB3.0 clock generator

Describe the 9FGV0841 PCIe and USB3.0 clock generator present on Ebisu
board. The clock generator supplies 100 MHz differential clock for both
PCIe slot and BT/WLAN expansion port, as well as for the USB 3.0 PHY.

This configuration is valid for SW49 in OFF position, which means the
PCIe signals are routed to the PCIe slot and U11 9FGV0841 PCIe clock
generator output 3 supplies clock to the PCIe slot.

In case the SW49 is set to ON position, which means the PCIe signals
are routed to the EX BT/WLAN expansion port, and U11 9FGV0841 PCIe
clock generator output 4 supplies clock to the port and &pciec0_rp
clocks should be changed to "clocks = <&pcie_usb_clk 4>;". Once the
BT/WLAN port is tested, this can be implemented using a DTO. Until
then, assume SW49 is set to OFF position.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260118135038.8033-10-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi
index 692a2b12aa035d5bc1b56bf480f9a54e94ca7a7c..aaedb1fb51aed41d2c8cdb2400fd2bbda1db573c 100644 (file)
--- a/arch/arm64/boot/dts/renesas/ebisu.dtsi
+++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi
@@ -53,6 +53,12 @@
                power-supply = <&reg_12p0v>;
        };
 
+       pcie_usb_refclk: clk-x7 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <25000000>;
+       };
+
        cvbs-in {
                compatible = "composite-video-connector";
                label = "CVBS IN";
@@ -439,6 +445,13 @@
                };
        };
 
+       pcie_usb_clk: clk@68 {
+               compatible = "renesas,9fgv0841";
+               reg = <0x68>;
+               clocks = <&pcie_usb_refclk>;
+               #clock-cells = <1>;
+       };
+
        video-receiver@70 {
                compatible = "adi,adv7482";
                reg = <0x70>;
@@ -577,13 +590,30 @@
 };
 
 &pcie_bus_clk {
-       clock-frequency = <100000000>;
+       status = "disabled";
 };
 
 &pciec0 {
+       clocks = <&cpg CPG_MOD 319>, <&pcie_usb_clk 1>;
        status = "okay";
 };
 
+&pciec0_rp {
+       /*
+        * This configuration is valid for SW49 in OFF position,
+        * which means the PCIe signals are routed to the PCIe slot
+        * and U11 9FGV0841 PCIe clock generator output 3 supplies
+        * clock to the PCIe slot.
+        *
+        * In case the SW49 is set to ON position, which means the
+        * PCIe signals are routed to the EX BT/WLAN expansion port,
+        * and U11 9FGV0841 PCIe clock generator output 4 supplies
+        * clock to the port, change clocks below to:
+        * clocks = <&pcie_usb_clk 4>;
+        */
+       clocks = <&pcie_usb_clk 3>;
+};
+
 &pfc {
        avb_pins: avb {
                groups = "avb_link", "avb_mii";
@@ -871,7 +901,18 @@
        status = "okay";
 };
 
+&usb3_phy0 {
+       clocks = <&pcie_usb_clk 6>;
+       status = "okay";
+};
+
+&usb3s0_clk {
+       status = "disabled";
+};
+
 &usb3_peri0 {
+       phys = <&usb3_phy0>;
+       phy-names = "usb";
        companion = <&xhci0>;
        status = "okay";
 };