x86: Add non-destructive source to @xorsign<mode>3_1

Add non-destructive source alternative to @xorsign<mode>3_1 for AVX.

gcc/

	PR target/89984
	* config/i386/i386-expand.c (ix86_split_xorsign): Use operands[2].
	* config/i386/i386.md (@xorsign<mode>3_1): Add non-destructive
	source alternative for AVX.

gcc/testsuite/

	PR target/89984
	* gcc.target/i386/pr89984-1.c: New test.
	* gcc.target/i386/pr89984-2.c: Likewise.
	* gcc.target/i386/xorsign-avx.c: Likewise.

diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index 2500dbfa7fb9d76869e7853bf302da5627c9be43..273a0ba8e3dc3ecb29c0603e3ba83fa653dc0f72 100644 (file)
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -2279,21 +2279,24 @@ void
 ix86_split_xorsign (rtx operands[])
 {
   machine_mode mode, vmode;
-  rtx dest, op0, mask, x;
+  rtx dest, op0, op1, mask, x;
 
   dest = operands[0];
   op0 = operands[1];
+  op1 = operands[2];
   mask = operands[3];
 
   mode = GET_MODE (dest);
   vmode = GET_MODE (mask);
 
-  dest = lowpart_subreg (vmode, dest, mode);
-  x = gen_rtx_AND (vmode, dest, mask);
-  emit_insn (gen_rtx_SET (dest, x));
+  op1 = lowpart_subreg (vmode, op1, mode);
+  x = gen_rtx_AND (vmode, op1, mask);
+  emit_insn (gen_rtx_SET (op1, x));
 
   op0 = lowpart_subreg (vmode, op0, mode);
-  x = gen_rtx_XOR (vmode, dest, op0);
+  x = gen_rtx_XOR (vmode, op1, op0);
+
+  dest = lowpart_subreg (vmode, dest, mode);
   emit_insn (gen_rtx_SET (dest, x));
 }
 

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 0cd151ce4e5d900e2576f978e495c334dd1cd301..18b91c77937271335698ff9d80de435405379e5d 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -10806,17 +10806,18 @@
   "ix86_expand_xorsign (operands); DONE;")
 
 (define_insn_and_split "@xorsign<mode>3_1"
-  [(set (match_operand:MODEF 0 "register_operand" "=Yv")
+  [(set (match_operand:MODEF 0 "register_operand" "=Yv,Yv")
        (unspec:MODEF
-         [(match_operand:MODEF 1 "register_operand" "Yv")
-          (match_operand:MODEF 2 "register_operand" "0")
-          (match_operand:<ssevecmode> 3 "nonimmediate_operand" "Yvm")]
+         [(match_operand:MODEF 1 "register_operand" "Yv,Yv")
+          (match_operand:MODEF 2 "register_operand" "0,Yv")
+          (match_operand:<ssevecmode> 3 "nonimmediate_operand" "Yvm,Yvm")]
          UNSPEC_XORSIGN))]
   "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
   "#"
   "&& reload_completed"
   [(const_int 0)]
-  "ix86_split_xorsign (operands); DONE;")
+  "ix86_split_xorsign (operands); DONE;"
+  [(set_attr "isa" "noavx,avx")])
 \f
 ;; One complement instructions
 

diff --git a/gcc/testsuite/gcc.target/i386/pr89984-1.c b/gcc/testsuite/gcc.target/i386/pr89984-1.c
new file mode 100644 (file)
index 0000000..d77691c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89984-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mno-avx -msse2" } */
+
+float
+check_f_pos (float x, float y)
+{
+  return x * __builtin_copysignf (1.0f, y);
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr89984-2.c b/gcc/testsuite/gcc.target/i386/pr89984-2.c
new file mode 100644 (file)
index 0000000..ff6a8e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89984-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mavx" } */
+
+float
+check_f_pos (float x, float y)
+{
+  return x * __builtin_copysignf (1.0f, y);
+}
+
+/* { dg-final { scan-assembler-not "vmovaps" } } */

diff --git a/gcc/testsuite/gcc.target/i386/xorsign-avx.c b/gcc/testsuite/gcc.target/i386/xorsign-avx.c
new file mode 100644 (file)
index 0000000..f2e2054
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/xorsign-avx.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target avx_runtime } } */
+/* { dg-options "-O2 -mavx -mfpmath=sse -ftree-vectorize" } */
+
+#include "xorsign.c"