ARM: dts: rockchip: Add D-PHY for RK3128

The InnoSilicon D-PHY found in RK3128 SoCs supports DSI/LVDS/TTL with a
maximum transfer rate of 1 Gbps per lane. While adding it, also add it's
clocks to RK3128_PD_VIO powerdomain as the phy is part of it.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20240509140653.168591-7-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index fb98873fd94e5994134a6107cadfeae57903ddb7..2e8ab8e8796a76d4b4d0268b220a8555257d37c9 100644 (file)
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -216,6 +216,8 @@
                                         <&cru ACLK_LCDC0>,
                                         <&cru HCLK_LCDC0>,
                                         <&cru PCLK_MIPI>,
+                                        <&cru PCLK_MIPIPHY>,
+                                        <&cru SCLK_MIPI_24M>,
                                         <&cru ACLK_RGA>,
                                         <&cru HCLK_RGA>,
                                         <&cru ACLK_VIO0>,
@@ -496,6 +498,18 @@
                };
        };
 
+       dphy: phy@20038000 {
+               compatible = "rockchip,rk3128-dsi-dphy";
+               reg = <0x20038000 0x4000>;
+               clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>;
+               clock-names = "ref", "pclk";
+               #phy-cells = <0>;
+               power-domains = <&power RK3128_PD_VIO>;
+               resets = <&cru SRST_MIPIPHY_P>;
+               reset-names = "apb";
+               status = "disabled";
+       };
+
        timer0: timer@20044000 {
                compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
                reg = <0x20044000 0x20>;