u16 family_id;
int extaddr;
int rawpage;
+ int cpu_port;
int page[RTMDIO_MAX_PORT];
bool raw[RTMDIO_MAX_PORT];
int smi_bus[RTMDIO_MAX_PORT];
if (priv->extaddr >= 0)
addr = priv->extaddr;
- if (addr >= RTMDIO_MAX_PORT)
+ if (addr >= priv->cpu_port)
return -ENODEV;
err = (*priv->read_mmd_phy)(addr, devnum, regnum, &val);
if (priv->extaddr >= 0)
addr = priv->extaddr;
- if (addr >= RTMDIO_MAX_PORT)
+ if (addr >= priv->cpu_port)
return -ENODEV;
if (addr >= 24 && addr <= 27 && priv->id == 0x8380)
if (priv->extaddr >= 0)
addr = priv->extaddr;
- if (addr >= RTMDIO_MAX_PORT)
+ if (addr >= priv->cpu_port)
return -ENODEV;
if (regnum == RTMDIO_PAGE_SELECT && priv->page[addr] != priv->rawpage)
if (priv->extaddr >= 0)
addr = priv->extaddr;
- if (addr >= RTMDIO_MAX_PORT)
+ if (addr >= priv->cpu_port)
return -ENODEV;
err = (*priv->write_mmd_phy)(addr, devnum, regnum, val);
if (priv->extaddr >= 0)
addr = priv->extaddr;
- if (addr >= RTMDIO_MAX_PORT)
+ if (addr >= priv->cpu_port)
return -ENODEV;
page = priv->page[addr];
if (priv->extaddr >= 0)
addr = priv->extaddr;
- if (addr >= RTMDIO_MAX_PORT)
+ if (addr >= priv->cpu_port)
return -ENODEV;
page = priv->page[addr];
bus_priv->write_mmd_phy = rtl838x_write_mmd_phy;
bus_priv->read_phy = rtl838x_read_phy;
bus_priv->write_phy = rtl838x_write_phy;
+ bus_priv->cpu_port = RTL838X_CPU_PORT;
bus_priv->rawpage = 0xfff;
break;
case RTL8390_FAMILY_ID:
bus_priv->write_mmd_phy = rtl839x_write_mmd_phy;
bus_priv->read_phy = rtl839x_read_phy;
bus_priv->write_phy = rtl839x_write_phy;
+ bus_priv->cpu_port = RTL839X_CPU_PORT;
bus_priv->rawpage = 0x1fff;
break;
case RTL9300_FAMILY_ID:
bus_priv->write_mmd_phy = rtl930x_write_mmd_phy;
bus_priv->read_phy = rtl930x_read_phy;
bus_priv->write_phy = rtl930x_write_phy;
+ bus_priv->cpu_port = RTL930X_CPU_PORT;
bus_priv->rawpage = 0xfff;
break;
case RTL9310_FAMILY_ID:
bus_priv->write_mmd_phy = rtl931x_write_mmd_phy;
bus_priv->read_phy = rtl931x_read_phy;
bus_priv->write_phy = rtl931x_write_phy;
+ bus_priv->cpu_port = RTL931X_CPU_PORT;
bus_priv->rawpage = 0x1fff;
break;
}
priv->mii_bus->read_c45 = rtmdio_read_c45;
priv->mii_bus->write_c45 = rtmdio_write_c45;
priv->mii_bus->parent = &priv->pdev->dev;
+ priv->mii_bus->phy_mask = ~(BIT_ULL(bus_priv->cpu_port) - 1ULL);
for_each_node_by_name(dn, "ethernet-phy") {
u32 smi_addr[2];