- 31-bit client programs are not supported.
- Hexadecimal floating point is not supported.
- Transactional memory is not supported.
-- Instructions operating on vector registers are not supported.
- memcheck, cachegrind, drd, helgrind, massif, lackey, and none are
supported.
- On machine models predating z10, cachegrind will assume a z10 cache
(1) Linux for zSeries ELF ABI Supplement
http://refspecs.linuxfoundation.org/ELF/zSeries/index.html
(2) z/Architecture Principles of Operation
- http://publibfi.boulder.ibm.com/epubs/pdf/dz9zr010.pdf
+ http://publibfi.boulder.ibm.com/epubs/pdf/dz9zr011.pdf
(3) z/Architecture Reference Summary
- http://publibfi.boulder.ibm.com/epubs/pdf/dz9zs008.pdf
+ http://publibfi.boulder.ibm.com/epubs/pdf/dz9zs009.pdf
{ VEX_HWCAPS_S390X_FPEXT, "fpext" },
{ VEX_HWCAPS_S390X_LSC, "lsc" },
{ VEX_HWCAPS_S390X_PFPO, "pfpo" },
+ { VEX_HWCAPS_S390X_VX, "vx" },
+ { VEX_HWCAPS_S390X_MSA5, "msa5" },
};
/* Allocate a large enough buffer */
static HChar buf[sizeof prefix +
#define VEX_S390X_MODEL_ZBC12 11
#define VEX_S390X_MODEL_Z13 12
#define VEX_S390X_MODEL_Z13S 13
-#define VEX_S390X_MODEL_UNKNOWN 14 /* always last in list */
+#define VEX_S390X_MODEL_Z14 14
+#define VEX_S390X_MODEL_Z14_ZR1 15
+#define VEX_S390X_MODEL_UNKNOWN 16 /* always last in list */
#define VEX_S390X_MODEL_MASK 0x3F
#define VEX_HWCAPS_S390X_LDISP (1<<6) /* Long-displacement facility */
{ "2828", VEX_S390X_MODEL_ZBC12 },
{ "2964", VEX_S390X_MODEL_Z13 },
{ "2965", VEX_S390X_MODEL_Z13S },
+ { "3906", VEX_S390X_MODEL_Z14 },
+ { "3907", VEX_S390X_MODEL_Z14_ZR1 },
};
Int model, n, fh;
--- /dev/null
+L1 topology: separate data and instruction; private
+L1 cache line size data: 256
+L1 cache line size insn: 256
+L1 total cachesize data: 131072
+L1 total cachesize insn: 131072
+L1 set. assoc. data: 8
+L1 set. assoc. insn: 8
+L2 topology: separate data and instruction; private
+L2 cache line size data: 256
+L2 cache line size insn: 256
+L2 total cachesize data: 4194304
+L2 total cachesize insn: 2097152
+L2 set. assoc. data: 8
+L2 set. assoc. insn: 8
+L3 topology: unified data and instruction; shared
+L3 cache line size data: 256
+L3 cache line size insn: 256
+L3 total cachesize data: 134217728
+L3 total cachesize insn: 134217728
+L3 set. assoc. data: 32
+L3 set. assoc. insn: 32
+L4 topology: unified data and instruction; shared
+L4 cache line size data: 256
+L4 cache line size insn: 256
+L4 total cachesize data: 704643072
+L4 total cachesize insn: 704643072
+L4 set. assoc. data: 42
+L4 set. assoc. insn: 42
{ "2828", "zBC12" },
{ "2964", "z13" },
{ "2965", "z13s" },
+ { "3906", "z14" },
+ { "3907", "z14 ZR1"},
};