x86/CPU/AMD: Add CPUID faulting support

Add CPUID faulting support on AMD using the same user interface.

Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/20250528213105.1149-1-bp@kernel.org

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index ee176236c2be99086ac9df76cf3208001a4c1dae..b78af55aa22e28d515dc985541f39bed948e4ce1 100644 (file)
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -457,9 +457,12 @@
 #define X86_FEATURE_WRMSR_XX_BASE_NS   (20*32+ 1) /* WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing */
 #define X86_FEATURE_LFENCE_RDTSC       (20*32+ 2) /* LFENCE always serializing / synchronizes RDTSC */
 #define X86_FEATURE_NULL_SEL_CLR_BASE  (20*32+ 6) /* Null Selector Clears Base */
+
 #define X86_FEATURE_AUTOIBRS           (20*32+ 8) /* Automatic IBRS */
 #define X86_FEATURE_NO_SMM_CTL_MSR     (20*32+ 9) /* SMM_CTL MSR is not present */
 
+#define X86_FEATURE_GP_ON_USER_CPUID   (20*32+17) /* User CPUID faulting */
+
 #define X86_FEATURE_PREFETCHI          (20*32+20) /* Prefetch Data/Instruction to Cache Level */
 #define X86_FEATURE_SBPB               (20*32+27) /* Selective Branch Prediction Barrier */
 #define X86_FEATURE_IBPB_BRTYPE                (20*32+28) /* MSR_PRED_CMD[IBPB] flushes all branch type predictions */

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index b7dded3c811328fae3fbfa2dc43ecceb212f2519..ff7e9743250fd90a7a2d711a87d2c8760e8f7c3f 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -830,6 +830,7 @@
 #define MSR_K7_HWCR_SMMLOCK            BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT)
 #define MSR_K7_HWCR_IRPERF_EN_BIT      30
 #define MSR_K7_HWCR_IRPERF_EN          BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)
+#define MSR_K7_HWCR_CPUID_USER_DIS_BIT 35
 #define MSR_K7_FID_VID_CTL             0xc0010041
 #define MSR_K7_FID_VID_STATUS          0xc0010042
 #define MSR_K7_HWCR_CPB_DIS_BIT                25

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 93da466dfe2cb5b057291c1e3cc29b7706a29f79..50f88fe51816556a99dcca62c511e24c420b15d3 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -489,6 +489,10 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
        }
 
        bsp_determine_snp(c);
+
+       if (cpu_has(c, X86_FEATURE_GP_ON_USER_CPUID))
+               setup_force_cpu_cap(X86_FEATURE_CPUID_FAULT);
+
        return;
 
 warn:

diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 704883c21f3a178dbc5ec24f9a8f4da2077f558e..7b94851bb37eb071878923307eed95d855ccb2b8 100644 (file)
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -334,13 +334,21 @@ DEFINE_PER_CPU(u64, msr_misc_features_shadow);
 
 static void set_cpuid_faulting(bool on)
 {
-       u64 msrval;
 
-       msrval = this_cpu_read(msr_misc_features_shadow);
-       msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
-       msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
-       this_cpu_write(msr_misc_features_shadow, msrval);
-       wrmsrq(MSR_MISC_FEATURES_ENABLES, msrval);
+       if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
+               u64 msrval;
+
+               msrval = this_cpu_read(msr_misc_features_shadow);
+               msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
+               msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
+               this_cpu_write(msr_misc_features_shadow, msrval);
+               wrmsrq(MSR_MISC_FEATURES_ENABLES, msrval);
+       } else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
+               if (on)
+                       msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_CPUID_USER_DIS_BIT);
+               else
+                       msr_clear_bit(MSR_K7_HWCR, MSR_K7_HWCR_CPUID_USER_DIS_BIT);
+       }
 }
 
 static void disable_cpuid(void)