perf/x86/intel: Update event constraints for PTL

Update perf hard-coded event constraints for Pantherlake according to
the latest PTL perfmon events (V1.05).

PTL has almost same perf event list as LNL except some PEBS event
constraints of E-core (exactly same on P-core). Define
intel_dkt_pebs_event_constraints[] to reflect the PTL E-core specific
PEBS event constraints.

PTL perfmon events:
https://github.com/intel/perfmon/blob/main/PTL/events/pantherlake_cougarcove_core.json
https://github.com/intel/perfmon/blob/main/PTL/events/pantherlake_darkmont_core.json

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260515061143.338553-9-dapeng1.mi@linux.intel.com

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 86ed34d2451cece24322283cb5595994963885fc..60a107c5b4d0f012f152dcd287d5154569c401c1 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -7790,6 +7790,13 @@ static __always_inline void intel_pmu_init_skt(struct pmu *pmu)
        static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
 }
 
+/* Hybrid client variant. */
+static __always_inline void intel_pmu_init_dkt_hybrid(struct pmu *pmu)
+{
+       intel_pmu_init_skt(pmu);
+       hybrid(pmu, pebs_constraints) = intel_dkt_pebs_event_constraints;
+}
+
 static __always_inline void intel_pmu_init_arw(struct pmu *pmu)
 {
        intel_pmu_init_grt(pmu);
@@ -8588,6 +8595,9 @@ __init int intel_pmu_init(void)
                /* Initialize big core specific PerfMon capabilities.*/
                pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
                intel_pmu_init_lnc(&pmu->pmu);
+               /* Initialize Atom core specific PerfMon capabilities.*/
+               pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
+               intel_pmu_init_dkt_hybrid(&pmu->pmu);
 
                goto lnl_common;
 
@@ -8602,6 +8612,9 @@ __init int intel_pmu_init(void)
                intel_pmu_init_lnc(&pmu->pmu);
                memcpy(hybrid_var(&pmu->pmu, hw_cache_extra_regs),
                       arl_lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
+               /* Initialize Atom core specific PerfMon capabilities.*/
+               pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
+               intel_pmu_init_skt(&pmu->pmu);
 
                goto lnl_common;
 
@@ -8614,6 +8627,9 @@ __init int intel_pmu_init(void)
                /* Initialize big core specific PerfMon capabilities.*/
                pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
                intel_pmu_init_lnc(&pmu->pmu);
+               /* Initialize Atom core specific PerfMon capabilities.*/
+               pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
+               intel_pmu_init_skt(&pmu->pmu);
 
        lnl_common:
 
@@ -8627,10 +8643,6 @@ __init int intel_pmu_init(void)
                extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
                        mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
 
-               /* Initialize Atom core specific PerfMon capabilities.*/
-               pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
-               intel_pmu_init_skt(&pmu->pmu);
-
                intel_pmu_pebs_data_source_lnl();
                break;
 

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index ce23b50f449add56e79533451a2c8ff2402e17eb..5159adabb9a2022f2a35299a5574991aa3db262f 100644 (file)
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -1303,6 +1303,13 @@ struct event_constraint intel_cmt_pebs_event_constraints[] = {
        EVENT_CONSTRAINT_END
 };
 
+struct event_constraint intel_dkt_pebs_event_constraints[] = {
+       /* Allow all events as PEBS with no flags */
+       INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xff),
+       INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xff),
+       EVENT_CONSTRAINT_END
+};
+
 struct event_constraint intel_arw_pebs_event_constraints[] = {
        /* Allow all events as PEBS with no flags */
        INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xff),

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index a9acfbe3c43537270e15a22ce79ea4cbf5e200b1..982864c7a06412559e643525ec06e94d4a38572b 100644 (file)
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -1712,6 +1712,8 @@ extern struct event_constraint intel_grt_pebs_event_constraints[];
 
 extern struct event_constraint intel_cmt_pebs_event_constraints[];
 
+extern struct event_constraint intel_dkt_pebs_event_constraints[];
+
 extern struct event_constraint intel_arw_pebs_event_constraints[];
 
 extern struct event_constraint intel_nehalem_pebs_event_constraints[];