]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
cxl/pci: Fix the incorrect check of pci_read_config_word() return
authorDave Jiang <dave.jiang@intel.com>
Thu, 4 Jun 2026 18:01:53 +0000 (11:01 -0700)
committerDave Jiang <dave.jiang@intel.com>
Thu, 4 Jun 2026 22:38:00 +0000 (15:38 -0700)
pci_read_config_word() returns PCIBIOS_* status on error which are
positive values. The check should be for non-zero values to indicate
error. Fix cxl_set_mem_enable() to check for non-zero return value
instead of negative value.

While fixing this, also convert the error to negative errno value when
returning on error path.

Fixes: 34e37b4c432c ("cxl/port: Enable HDM Capability after validating DVSEC Ranges")
Reviewed-by: Richard Cheng <icheng@nvidia.com>
Reviewed-by: Jonathan Cameron <jic23@kernel.org>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Assisted-by: Claude:claude-opus-4-8
Link: https://patch.msgid.link/20260604180154.1925149-2-dave.jiang@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
drivers/cxl/core/pci.c

index d1f487b3d809adde0010ae8bc6838e620d7d321a..43885c59a7f2461f1834cdfcec5eab9390415f86 100644 (file)
@@ -187,8 +187,8 @@ static int cxl_set_mem_enable(struct cxl_dev_state *cxlds, u16 val)
        int rc;
 
        rc = pci_read_config_word(pdev, d + PCI_DVSEC_CXL_CTRL, &ctrl);
-       if (rc < 0)
-               return rc;
+       if (rc)
+               return pcibios_err_to_errno(rc);
 
        if ((ctrl & PCI_DVSEC_CXL_MEM_ENABLE) == val)
                return 1;
@@ -196,8 +196,8 @@ static int cxl_set_mem_enable(struct cxl_dev_state *cxlds, u16 val)
        ctrl |= val;
 
        rc = pci_write_config_word(pdev, d + PCI_DVSEC_CXL_CTRL, ctrl);
-       if (rc < 0)
-               return rc;
+       if (rc)
+               return pcibios_err_to_errno(rc);
 
        return 0;
 }