perf/x86/intel: Update event constraints and cache_extra_regsfor CWF

Update perf hard-coded event constraints and cache_extra_regs[] for
Clearwater Forest according to the latest CWF perfmon events (V1.02).

An important difference is that CWF introduce new extra register values
for the L3 cache OCR events, so define darkmont specific
dkt_hw_cache_extra_regs[] array.

CWF perfmon events:
https://github.com/intel/perfmon/blob/main/CWF/events/clearwaterforest_core.json

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260515061143.338553-12-dapeng1.mi@linux.intel.com

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index c4efb87eea9a4bbeb178871a5d929fa1eb248e74..0217e701aeebb9f1bc51e31103d12c439d6dc040 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2582,6 +2582,22 @@ static __initconst const u64 skt_hw_cache_extra_regs
        },
 };
 
+static __initconst const u64 dkt_hw_cache_extra_regs
+                               [PERF_COUNT_HW_CACHE_MAX]
+                               [PERF_COUNT_HW_CACHE_OP_MAX]
+                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+       [C(LL)] = {
+               [C(OP_READ)] = {
+                       [C(RESULT_ACCESS)]      = 0x10001,              /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
+                       [C(RESULT_MISS)]        = 0x33FBFC00001,        /* OCR.DEMAND_DATA_RD.L3_MISS */
+               },
+               [C(OP_WRITE)] = {
+                       [C(RESULT_ACCESS)]      = 0x10002,              /* OCR.DEMAND_RFO.ANY_RESPONSE */
+                       [C(RESULT_MISS)]        = 0x33FBFC00002,        /* OCR.DEMAND_RFO.L3_MISS */
+               },
+       },
+};
+
 static __initconst const u64 arw_hw_cache_extra_regs
                                [PERF_COUNT_HW_CACHE_MAX]
                                [PERF_COUNT_HW_CACHE_OP_MAX]
@@ -7814,6 +7830,18 @@ static __always_inline void intel_pmu_init_dkt_hybrid(struct pmu *pmu)
        hybrid(pmu, pebs_constraints) = intel_dkt_pebs_event_constraints;
 }
 
+/*
+ * Darkmont is used by the CWF and PTL E-cores, but their L3 OCR
+ * events require different extra MSR values. Keep a separate init
+ * function for the non-hybrid server variant.
+ */
+static __always_inline void intel_pmu_init_dkt(struct pmu *pmu)
+{
+       intel_pmu_init_dkt_hybrid(pmu);
+       memcpy(hybrid_var(pmu, hw_cache_extra_regs),
+              dkt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
+}
+
 static __always_inline void intel_pmu_init_arw(struct pmu *pmu)
 {
        intel_pmu_init_grt(pmu);
@@ -8148,7 +8176,7 @@ __init int intel_pmu_init(void)
                break;
 
        case INTEL_ATOM_DARKMONT_X:
-               intel_pmu_init_skt(NULL);
+               intel_pmu_init_dkt(NULL);
                intel_pmu_pebs_data_source_cmt();
                x86_pmu.pebs_latency_data = cmt_latency_data;
                x86_pmu.get_event_constraints = cmt_get_event_constraints;