gpio: brcmstb: implement .irq_mask_ack()

The .irq_mask_ack() operation is slightly more efficient than doing
.irq_mask() and .irq_ack() separately.

More importantly for this driver it bypasses the check of
irqd_irq_masked ensuring a previously masked but still active
interrupt gets remasked if unmasked at the hardware level. This
allows the driver to more efficiently unmask the wake capable
interrupts when quiescing without needing to enable the irqs
individually to clear the irqd_irq_masked state.

Reviewed-by: Linus Walleij <linusw@kernel.org>
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Signed-off-by: Doug Berger <opendmb@gmail.com>
Co-developed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://patch.msgid.link/20260204164333.1146039-3-florian.fainelli@broadcom.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>

diff --git a/drivers/gpio/gpio-brcmstb.c b/drivers/gpio/gpio-brcmstb.c
index 4c35ed664f65317c1dde170c19d7037c7ff650cb..7ebf1217f383d095c76f1ea47d1aa30ce89ad2be 100644 (file)
--- a/drivers/gpio/gpio-brcmstb.c
+++ b/drivers/gpio/gpio-brcmstb.c
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// Copyright (C) 2015-2017 Broadcom
+// Copyright (C) 2015-2017, 2026 Broadcom
 
 #include <linux/bitops.h>
 #include <linux/gpio/driver.h>
@@ -95,15 +95,13 @@ static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
        return hwirq - bank->chip.gc.offset;
 }
 
-static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
-                                  irq_hw_number_t hwirq, bool enable)
+static void __brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
+                                    irq_hw_number_t hwirq, bool enable)
 {
        struct brcmstb_gpio_priv *priv = bank->parent_priv;
        u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
        u32 imask;
 
-       guard(gpio_generic_lock_irqsave)(&bank->chip);
-
        imask = gpio_generic_read_reg(&bank->chip,
                                      priv->reg_base + GIO_MASK(bank->id));
        if (enable)
@@ -114,6 +112,13 @@ static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
                               priv->reg_base + GIO_MASK(bank->id), imask);
 }
 
+static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
+                                  irq_hw_number_t hwirq, bool enable)
+{
+       guard(gpio_generic_lock_irqsave)(&bank->chip);
+       __brcmstb_gpio_set_imask(bank, hwirq, enable);
+}
+
 static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 {
        struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
@@ -135,6 +140,20 @@ static void brcmstb_gpio_irq_mask(struct irq_data *d)
        brcmstb_gpio_set_imask(bank, irqd_to_hwirq(d), false);
 }
 
+static void brcmstb_gpio_irq_mask_ack(struct irq_data *d)
+{
+       struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+       struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
+       struct brcmstb_gpio_priv *priv = bank->parent_priv;
+       irq_hw_number_t hwirq = irqd_to_hwirq(d);
+       u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
+
+       guard(gpio_generic_lock_irqsave)(&bank->chip);
+       __brcmstb_gpio_set_imask(bank, hwirq, false);
+       gpio_generic_write_reg(&bank->chip,
+                              priv->reg_base + GIO_STAT(bank->id), mask);
+}
+
 static void brcmstb_gpio_irq_unmask(struct irq_data *d)
 {
        struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
@@ -471,6 +490,7 @@ static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
        priv->irq_chip.name = dev_name(dev);
        priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
        priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
+       priv->irq_chip.irq_mask_ack = brcmstb_gpio_irq_mask_ack;
        priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
        priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
        priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;