arm: dts: stm32: introduce the debug bus for stm32mp1x platforms

Some peripherals cannot be probed if a debug configuration is not set
in the BSEC.
Introduce a debug bus that will check the debug subsystem accessibility
before probing these peripheral drivers.

Add Coresight peripheral nodes under this bus and add the appropriate
access-controllers property to the HDP node.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Link: https://lore.kernel.org/r/20260226-debug_bus-v6-7-5d794697798d@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi
index b9657ff91c234a664218ccc7469a717a48152c85..a2513d55499ff8b492ed34af96023855db64b13e 100644 (file)
--- a/arch/arm/boot/dts/st/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
@@ -3,6 +3,7 @@
  * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
  */
+#include <dt-bindings/arm/coresight-cti-dt.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/stm32mp13-clks.h>
 #include <dt-bindings/reset/stm32mp13-resets.h>
@@ -964,9 +965,125 @@
                        compatible = "st,stm32mp131-hdp";
                        reg = <0x5002a000 0x400>;
                        clocks = <&rcc HDP>;
+                       access-controllers = <&dbg_bus 1>;
                        status = "disabled";
                };
 
+               dbg_bus: bus@50080000 {
+                       compatible = "st,stm32mp131-dbg-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       #access-controller-cells = <1>;
+                       ranges = <0x50080000 0x50080000 0x3f80000>;
+                       status = "disabled";
+
+                       cs_etf: etf@50092000 {
+                               compatible = "arm,coresight-tmc", "arm,primecell";
+                               reg = <0x50092000 0x1000>;
+                               clocks = <&rcc CK_DBG>;
+                               clock-names = "apb_pclk";
+                               access-controllers = <&dbg_bus 0>;
+                               status = "disabled";
+
+                               in-ports {
+                                       port {
+                                               etf_in_port: endpoint {
+                                                       remote-endpoint = <&etm0_out_port>;
+                                               };
+                                       };
+                               };
+
+                               out-ports {
+                                       port {
+                                               etf_out_port: endpoint {
+                                                       remote-endpoint = <&tpiu_in_port>;
+                                               };
+                                       };
+                               };
+                       };
+
+                       cs_tpiu: tpiu@50093000 {
+                               compatible = "arm,coresight-tpiu", "arm,primecell";
+                               reg = <0x50093000 0x1000>;
+                               clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+                               clock-names = "apb_pclk", "atclk";
+                               access-controllers = <&dbg_bus 0>;
+                               status = "disabled";
+
+                               in-ports {
+                                       port {
+                                               tpiu_in_port: endpoint {
+                                                       remote-endpoint = <&etf_out_port>;
+                                               };
+                                       };
+                               };
+                       };
+
+                       cs_cti_trace: cti@50094000 {
+                               compatible = "arm,coresight-cti", "arm,primecell";
+                               reg = <0x50094000 0x1000>;
+                               clocks = <&rcc CK_DBG>;
+                               clock-names = "apb_pclk";
+                               access-controllers = <&dbg_bus 0>;
+                               status = "disabled";
+                       };
+
+                       cs_cti_cpu0: cti@500d8000 {
+                               compatible = "arm,coresight-cti", "arm,primecell";
+                               reg = <0x500d8000 0x1000>;
+                               clocks = <&rcc CK_DBG>;
+                               clock-names = "apb_pclk";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               access-controllers = <&dbg_bus 0>;
+                               status = "disabled";
+
+                               trig-conns@0 {
+                                       reg = <0>;
+                                       arm,trig-in-sigs = <0 4 5>;
+                                       arm,trig-in-types = <PE_DBGTRIGGER
+                                                            GEN_IO
+                                                            GEN_IO>;
+                                       arm,trig-out-sigs = <0 7>;
+                                       arm,trig-out-types = <PE_EDBGREQ
+                                                             PE_DBGRESTART>;
+                                       cpu = <&cpu0>;
+                               };
+
+                               trig-conns@2 {
+                                       reg = <2>;
+                                       arm,trig-in-sigs = <2 3 6>;
+                                       arm,trig-in-types = <ETM_EXTOUT
+                                                            ETM_EXTOUT
+                                                            ETM_EXTOUT>;
+                                       arm,trig-out-sigs = <1 2 3 4>;
+                                       arm,trig-out-types = <ETM_EXTIN
+                                                             ETM_EXTIN
+                                                             ETM_EXTIN
+                                                             ETM_EXTIN>;
+                                       arm,cs-dev-assoc = <&cs_etm0>;
+                               };
+                       };
+
+                       cs_etm0: etm@500dc000 {
+                               compatible = "arm,coresight-etm3x", "arm,primecell";
+                               reg = <0x500dc000 0x1000>;
+                               cpu = <&cpu0>;
+                               clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+                               clock-names = "apb_pclk", "atclk";
+                               access-controllers = <&dbg_bus 0>;
+                               status = "disabled";
+
+                               out-ports {
+                                       port {
+                                               etm0_out_port: endpoint {
+                                                       remote-endpoint = <&etf_in_port>;
+                                               };
+                                       };
+                               };
+                       };
+               };
+
                mdma: dma-controller@58000000 {
                        compatible = "st,stm32h7-mdma";
                        reg = <0x58000000 0x1000>;

diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi
index 85cb0f16ca73bfe4ae8aa8b990880889d7377414..075a2b433172b04d503f44ec6eca880706f53a2f 100644 (file)
--- a/arch/arm/boot/dts/st/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
@@ -3,6 +3,7 @@
  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
  */
+#include <dt-bindings/arm/coresight-cti-dt.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/stm32mp1-clks.h>
 #include <dt-bindings/reset/stm32mp1-resets.h>
@@ -282,9 +283,180 @@
                        compatible = "st,stm32mp151-hdp";
                        reg = <0x5002a000 0x400>;
                        clocks = <&rcc HDP>;
+                       access-controllers = <&dbg_bus 1>;
                        status = "disabled";
                };
 
+               dbg_bus: bus@50080000 {
+                       compatible = "st,stm32mp151-dbg-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       #access-controller-cells = <1>;
+                       ranges = <0x50080000 0x50080000 0x3f80000>,
+                                <0x90000000 0x90000000 0x1000000>;
+                       status = "disabled";
+
+                       cs_funnel: funnel@50091000 {
+                               compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+                               reg = <0x50091000 0x1000>;
+                               clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+                               clock-names = "apb_pclk", "atclk";
+                               access-controllers = <&dbg_bus 0>;
+                               status = "disabled";
+
+                               in-ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       port@0 {
+                                               reg = <0>;
+                                               funnel_in_port0: endpoint {
+                                                       remote-endpoint = <&stm_out_port>;
+                                               };
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+                                               funnel_in_port1: endpoint {
+                                                       remote-endpoint = <&etm0_out>;
+                                               };
+                                       };
+                               };
+
+                               out-ports {
+                                       port {
+                                               funnel_out_port: endpoint {
+                                                       remote-endpoint = <&etf_in_port>;
+                                               };
+                                       };
+                               };
+                       };
+
+                       cs_etf: etf@50092000 {
+                               compatible = "arm,coresight-tmc", "arm,primecell";
+                               reg = <0x50092000 0x1000>;
+                               clocks = <&rcc CK_DBG>;
+                               clock-names = "apb_pclk";
+                               access-controllers = <&dbg_bus 0>;
+                               status = "disabled";
+
+                               in-ports {
+                                       port {
+                                               etf_in_port: endpoint {
+                                                       remote-endpoint = <&funnel_out_port>;
+                                               };
+                                       };
+                               };
+
+                               out-ports {
+                                       port {
+                                               etf_out_port: endpoint {
+                                                       remote-endpoint = <&tpiu_in_port>;
+                                               };
+                                       };
+                               };
+                       };
+
+                       cs_tpiu: tpiu@50093000 {
+                               compatible = "arm,coresight-tpiu", "arm,primecell";
+                               reg = <0x50093000 0x1000>;
+                               clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+                               clock-names = "apb_pclk", "atclk";
+                               access-controllers = <&dbg_bus 0>;
+                               status = "disabled";
+
+                               in-ports {
+                                       port {
+                                               tpiu_in_port: endpoint {
+                                                       remote-endpoint = <&etf_out_port>;
+                                               };
+                                       };
+                               };
+                       };
+
+                       cs_cti_trace: cti@50094000 {
+                               compatible = "arm,coresight-cti", "arm,primecell";
+                               reg = <0x50094000 0x1000>;
+                               clocks = <&rcc CK_DBG>;
+                               clock-names = "apb_pclk";
+                               access-controllers = <&dbg_bus 0>;
+                               status = "disabled";
+                       };
+
+                       cs_stm: stm@500a0000 {
+                               compatible = "arm,coresight-stm", "arm,primecell";
+                               reg = <0x500a0000 0x00001000>,
+                                     <0x90000000 0x01000000>;
+                               reg-names = "stm-base", "stm-stimulus-base";
+                               clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+                               clock-names = "apb_pclk", "atclk";
+                               access-controllers = <&dbg_bus 0>;
+                               status = "disabled";
+
+                               out-ports {
+                                       port {
+                                               stm_out_port: endpoint {
+                                                       remote-endpoint = <&funnel_in_port0>;
+                                               };
+                                       };
+                               };
+                       };
+
+                       cs_cti_cpu0: cti@500d8000 {
+                               compatible = "arm,coresight-cti", "arm,primecell";
+                               reg = <0x500d8000 0x1000>;
+                               clocks = <&rcc CK_DBG>;
+                               clock-names = "apb_pclk";
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               access-controllers = <&dbg_bus 0>;
+                               status = "disabled";
+
+                               trig-conns@0 {
+                                       reg = <0>;
+                                       arm,trig-in-sigs = <0 4 5>;
+                                       arm,trig-in-types = <PE_DBGTRIGGER
+                                                            GEN_IO
+                                                            GEN_IO>;
+                                       arm,trig-out-sigs = <0 7>;
+                                       arm,trig-out-types = <PE_EDBGREQ
+                                                             PE_DBGRESTART>;
+                                       cpu = <&cpu0>;
+                               };
+
+                               trig-conns@2 {
+                                       reg = <2>;
+                                       arm,trig-in-sigs = <2 3 6>;
+                                       arm,trig-in-types = <ETM_EXTOUT
+                                                            ETM_EXTOUT
+                                                            ETM_EXTOUT>;
+                                       arm,trig-out-sigs = <1 2 3 4>;
+                                       arm,trig-out-types = <ETM_EXTIN
+                                                             ETM_EXTIN
+                                                             ETM_EXTIN
+                                                             ETM_EXTIN>;
+                                       arm,cs-dev-assoc = <&cs_etm0>;
+                               };
+                       };
+
+                       cs_etm0: etm@500dc000 {
+                               compatible = "arm,coresight-etm3x", "arm,primecell";
+                               reg = <0x500dc000 0x1000>;
+                               cpu = <&cpu0>;
+                               clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+                               clock-names = "apb_pclk", "atclk";
+                               access-controllers = <&dbg_bus 0>;
+                               status = "disabled";
+
+                               out-ports {
+                                       port {
+                                               etm0_out: endpoint {
+                                                       remote-endpoint = <&funnel_in_port1>;
+                                               };
+                                       };
+                               };
+                       };
+               };
+
                mdma1: dma-controller@58000000 {
                        compatible = "st,stm32h7-mdma";
                        reg = <0x58000000 0x1000>;

diff --git a/arch/arm/boot/dts/st/stm32mp153.dtsi b/arch/arm/boot/dts/st/stm32mp153.dtsi
index 92794b942ab22920c72859970127db4f01e53e5d..17d52d93695e14e0e9d8ff9a57bc86f5f5d56e77 100644 (file)
--- a/arch/arm/boot/dts/st/stm32mp153.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp153.dtsi
@@ -30,6 +30,74 @@
        };
 };
 
+&cs_funnel {
+       in-ports {
+               port@2 {
+                       reg = <2>;
+                       funnel_in_port2: endpoint {
+                               remote-endpoint = <&etm1_out>;
+                       };
+               };
+       };
+};
+
+&dbg_bus {
+       cs_cti_cpu1: cti@500d9000 {
+               compatible = "arm,coresight-cti", "arm,primecell";
+               reg = <0x500d9000 0x1000>;
+               clocks = <&rcc CK_DBG>;
+               clock-names = "apb_pclk";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               access-controllers = <&dbg_bus 0>;
+               status = "disabled";
+
+               trig-conns@0 {
+                       reg = <0>;
+                       arm,trig-in-sigs = <0 4 5>;
+                       arm,trig-in-types = <PE_DBGTRIGGER
+                                            GEN_IO
+                                            GEN_IO>;
+                       arm,trig-out-sigs = <0 7>;
+                       arm,trig-out-types = <PE_EDBGREQ
+                                             PE_DBGRESTART>;
+                       cpu = <&cpu1>;
+               };
+
+               trig-conns@2 {
+                       reg = <2>;
+                       arm,trig-in-sigs = <2 3 6>;
+                       arm,trig-in-types = <ETM_EXTOUT
+                                            ETM_EXTOUT
+                                            ETM_EXTOUT>;
+                       arm,trig-out-sigs = <1 2 3 4>;
+                       arm,trig-out-types = <ETM_EXTIN
+                                             ETM_EXTIN
+                                             ETM_EXTIN
+                                             ETM_EXTIN>;
+                       arm,cs-dev-assoc = <&cs_etm1>;
+               };
+       };
+
+       cs_etm1: etm@500dd000 {
+               compatible = "arm,coresight-etm3x", "arm,primecell";
+               reg = <0x500dd000 0x1000>;
+               cpu = <&cpu1>;
+               clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>;
+               clock-names = "apb_pclk", "atclk";
+               access-controllers = <&dbg_bus 0>;
+               status = "disabled";
+
+               out-ports {
+                       port {
+                               etm1_out: endpoint {
+                                       remote-endpoint = <&funnel_in_port2>;
+                               };
+                       };
+               };
+       };
+};
+
 &etzpc {
        m_can1: can@4400e000 {
                compatible = "bosch,m_can";