]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
[PATCH] RISC-V: Add missing insn types for XiangShan Nanhu scheduler model
authorZhao Dingyi <dingyizhao.zdy@outlook.com>
Sat, 7 Sep 2024 16:48:46 +0000 (10:48 -0600)
committerJeff Law <jlaw@ventanamicro.com>
Sat, 7 Sep 2024 16:48:46 +0000 (10:48 -0600)
This patch aims to add the missing instruction types to the XiangShan-Nanhu scheduler model.

The current XiangShan -Nanhu model lacks the trap, atomic trap, fcvt_i2f, and fcvt_f2i instructions.

The trap, atomic, and i2f instructions belong to xs_jmp_rs. [1]

The f2i instruction belongs to xs_fmisc_rs.[2]

[1]
https://github.com/OpenXiangShan/XiangShan/blob/v2.0/src/main/scala/xiangshan/package.scala#L780

[2]
https://github.com/OpenXiangShan/XiangShan/blob/v2.0/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala#L290

gcc/ChangeLog:

* config/riscv/xiangshan.md: Add atomic, trap, fcvt_i2f, fcvt_f2i.

gcc/config/riscv/xiangshan.md

index 76539d332b82e477f603bfd432ebd3ccfca20aaa..eb83bbff1bebc0e374ee4b691eb2762e1d834784 100644 (file)
 
 (define_insn_reservation "xiangshan_jump" 1
   (and (eq_attr "tune" "xiangshan")
-       (eq_attr "type" "jump,call,auipc,unknown,branch,jalr,ret,sfb_alu"))
+       (eq_attr "type" "jump,call,auipc,unknown,branch,jalr,ret,sfb_alu,trap"))
   "xs_jmp_rs")
 
 (define_insn_reservation "xiangshan_i2f" 3
   (and (eq_attr "tune" "xiangshan")
-       (eq_attr "type" "mtc"))
+       (eq_attr "type" "mtc,fcvt_i2f"))
+  "xs_jmp_rs")
+
+(define_insn_reservation "xiangshan_atomic" 1
+  (and (eq_attr "tune" "xiangshan")
+       (eq_attr "type" "atomic"))
   "xs_jmp_rs")
 
 (define_insn_reservation "xiangshan_mul" 3
 
 (define_insn_reservation "xiangshan_f2f" 3
   (and (eq_attr "tune" "xiangshan")
-       (eq_attr "type" "fcvt,fmove"))
+       (eq_attr "type" "fcvt,fcvt_f2i,fmove"))
   "xs_fmisc_rs")
 
 (define_insn_reservation "xiangshan_f2i" 3