aarch64: PR target/99195 annotate qabs,qneg patterns for vec-concat-zero

Straightforward like previous patches in this series.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.

gcc/ChangeLog:

	PR target/99195
	* config/aarch64/aarch64-simd.md (aarch64_s<optab><mode>): Rename to...
	(aarch64_s<optab><mode><vczle><vczbe>): ... This.

gcc/testsuite/ChangeLog:

	PR target/99195
	* gcc.target/aarch64/simd/pr99195_4.c: Add testing for qabs, qneg.

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index bfc98a8d943467b33390defab9682f44efab5907..26320f2e3922c0b7d3780ac34b7fef6be51b7dc8 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -5377,7 +5377,7 @@
 
 ;; <su>q<absneg>
 
-(define_insn "aarch64_s<optab><mode>"
+(define_insn "aarch64_s<optab><mode><vczle><vczbe>"
   [(set (match_operand:VSDQ_I 0 "register_operand" "=w")
        (UNQOPS:VSDQ_I
          (match_operand:VSDQ_I 1 "register_operand" "w")))]

diff --git a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_4.c b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_4.c
index 8faf5691661eb55e304dcc564e8d8089a1f2f75c..698da8683ad737660eddc69735bed4f4966b6175 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/simd/pr99195_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/pr99195_4.c
@@ -50,6 +50,16 @@ MYOP (uint32x4_t, uint64x2_t, uint32x2_t, OP, u64, u32)      \
 FUNC (movn)
 FUNC (qmovn)
 
+#undef FUNC
+#define FUNC(OP)                                       \
+MYOP (int8x16_t, int8x8_t, int8x8_t, OP, s8, s8)       \
+MYOP (int16x8_t, int16x4_t, int16x4_t, OP, s16, s16)   \
+MYOP (int32x4_t, int32x2_t, int32x2_t, OP, s32, s32)   \
+MYOP (int64x2_t, int64x1_t, int64x1_t, OP, s64, s64)   \
+
+FUNC (qabs)
+FUNC (qneg)
+
 #undef FUNC
 #define FUNC(OP)                                       \
 MYOP (uint8x16_t, int16x8_t, uint8x8_t, OP, s16, u8)   \