rs6000-c.c (rs6000_cpu_cpp_builtins): Provide builtin define __VEC_ELEMENT_REG_ORDER__.

2014-08-20  Bill Schmidt  <wschmidt@vnet.ibm.com>

	* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Provide
	builtin define __VEC_ELEMENT_REG_ORDER__.

From-SVN: r214236

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8f9b113e4dab22e32f3b5cab1709fabc485a0a82..7742b84a783607f8c87fae9934c4f0737da4dd37 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2014-08-20  Bill Schmidt  <wschmidt@vnet.ibm.com>
+
+       * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Provide
+       builtin define __VEC_ELEMENT_REG_ORDER__.
+
 2014-08-20  Martin Jambor  <mjambor@suse.cz>
            Wei Mi  <wmi@google.com>
 

diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 2b9cf7a0b383706efd895c59a3b7ab71584d926b..40a17e26418f27480a747be0bdfc9c702b949746 100644 (file)
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -497,6 +497,12 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile)
       break;
     }
 
+  /* Vector element order.  */
+  if (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2))
+    builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_BIG_ENDIAN__");
+  else
+    builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_LITTLE_ENDIAN__");
+
   /* Let the compiled code know if 'f' class registers will not be available.  */
   if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
     builtin_define ("__NO_FPRS__");