intel_uncore.o \
intel_uncore_trace.o \
intel_wakeref.o \
- vlv_sideband.o \
+ vlv_iosf_sb.o \
vlv_suspend.o
# core peripheral code
#include "intel_mchbar_regs.h"
#include "intel_wm.h"
#include "skl_watermark.h"
-#include "vlv_sideband.h"
+#include "vlv_iosf_sb.h"
struct intel_watermark_params {
u16 fifo_size;
#include "skl_watermark.h"
#include "skl_watermark_regs.h"
#include "vlv_dsi.h"
-#include "vlv_sideband.h"
+#include "vlv_iosf_sb.h"
/**
* DOC: CDCLK / RAWCLK
#include "vlv_dsi.h"
#include "vlv_dsi_pll.h"
#include "vlv_dsi_regs.h"
-#include "vlv_sideband.h"
+#include "vlv_iosf_sb.h"
static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
#include "intel_snps_phy.h"
#include "skl_watermark.h"
#include "skl_watermark_regs.h"
-#include "vlv_sideband.h"
+#include "vlv_iosf_sb.h"
#define for_each_power_domain_well(__display, __power_well, __domain) \
for_each_power_well((__display), __power_well) \
#include "intel_display_power_map.h"
#include "intel_display_power_well.h"
#include "intel_display_types.h"
-#include "vlv_sideband_reg.h"
+#include "vlv_iosf_sb_reg.h"
#define __LIST_INLINE_ELEMS(__elem_type, ...) \
((__elem_type[]) { __VA_ARGS__ })
#include "intel_vga.h"
#include "skl_watermark.h"
#include "vlv_dpio_phy_regs.h"
-#include "vlv_sideband.h"
-#include "vlv_sideband_reg.h"
+#include "vlv_iosf_sb.h"
+#include "vlv_iosf_sb_reg.h"
struct i915_power_well_regs {
i915_reg_t bios;
#include "intel_dp.h"
#include "intel_dpio_phy.h"
#include "vlv_dpio_phy_regs.h"
-#include "vlv_sideband.h"
+#include "vlv_iosf_sb.h"
/**
* DOC: DPIO
#include "intel_pps.h"
#include "intel_snps_phy.h"
#include "vlv_dpio_phy_regs.h"
-#include "vlv_sideband.h"
+#include "vlv_iosf_sb.h"
struct intel_dpll_funcs {
int (*crtc_compute_clock)(struct intel_atomic_state *state,
#include "intel_pps_regs.h"
#include "vlv_dsi.h"
#include "vlv_dsi_regs.h"
-#include "vlv_sideband.h"
+#include "vlv_iosf_sb.h"
#define MIPI_TRANSFER_MODE_SHIFT 0
#define MIPI_VIRTUAL_CHANNEL_SHIFT 1
#include "vlv_dsi.h"
#include "vlv_dsi_pll.h"
#include "vlv_dsi_regs.h"
-#include "vlv_sideband.h"
+#include "vlv_iosf_sb.h"
/* return pixels in terms of txbyteclkhs */
static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
#include "intel_dsi.h"
#include "vlv_dsi_pll.h"
#include "vlv_dsi_pll_regs.h"
-#include "vlv_sideband.h"
+#include "vlv_iosf_sb.h"
static const u16 lfsr_converts[] = {
426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
#include "intel_rps.h"
#include "intel_runtime_pm.h"
#include "intel_uncore.h"
-#include "vlv_sideband.h"
+#include "vlv_iosf_sb.h"
void intel_gt_pm_debugfs_forcewake_user_open(struct intel_gt *gt)
{
#include "intel_mchbar_regs.h"
#include "intel_pcode.h"
#include "intel_rps.h"
-#include "vlv_sideband.h"
+#include "vlv_iosf_sb.h"
#include "../../../platform/x86/intel_ips.h"
#define BUSY_MAX_EI 20u /* ms */
#include "intel_pcode.h"
#include "intel_region_ttm.h"
#include "intel_sbi.h"
-#include "vlv_sideband.h"
+#include "vlv_iosf_sb.h"
#include "vlv_suspend.h"
static const struct drm_driver i915_drm_driver;
#include "i915_reg.h"
#include "intel_clock_gating.h"
#include "intel_mchbar_regs.h"
-#include "vlv_sideband.h"
+#include "vlv_iosf_sb.h"
struct drm_i915_clock_gating_funcs {
void (*init_clock_gating)(struct drm_i915_private *i915);
#include "intel_dram.h"
#include "intel_mchbar_regs.h"
#include "intel_pcode.h"
-#include "vlv_sideband.h"
+#include "vlv_iosf_sb.h"
struct dram_dimm_info {
u16 size;
#include "i915_drv.h"
#include "i915_iosf_mbi.h"
#include "i915_reg.h"
-#include "vlv_sideband.h"
+#include "vlv_iosf_sb.h"
#include "display/intel_dpio_phy.h"
* Copyright © 2013-2021 Intel Corporation
*/
-#ifndef _VLV_SIDEBAND_H_
-#define _VLV_SIDEBAND_H_
+#ifndef _VLV_IOSF_SB_H_
+#define _VLV_IOSF_SB_H_
#include <linux/bitops.h>
#include <linux/types.h>
-#include "vlv_sideband_reg.h"
+#include "vlv_iosf_sb_reg.h"
enum dpio_phy;
struct drm_i915_private;
vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
}
-#endif /* _VLV_SIDEBAND_H_ */
+#endif /* _VLV_IOSF_SB_H_ */
* Copyright © 2022 Intel Corporation
*/
-#ifndef _VLV_SIDEBAND_REG_H_
-#define _VLV_SIDEBAND_REG_H_
+#ifndef _VLV_IOSF_SB_REG_H_
+#define _VLV_IOSF_SB_REG_H_
/* See configdb bunit SB addr map */
#define BUNIT_REG_BISOC 0x11
#define CCK_FREQUENCY_STATUS_SHIFT 8
#define CCK_FREQUENCY_VALUES (0x1f << 0)
-#endif /* _VLV_SIDEBAND_REG_H_ */
+#endif /* _VLV_IOSF_SB_REG_H_ */
* Copyright © 2013-2021 Intel Corporation
*/
-#ifndef _VLV_SIDEBAND_H_
-#define _VLV_SIDEBAND_H_
+#ifndef _VLV_IOSF_SB_H_
+#define _VLV_IOSF_SB_H_
#include <linux/types.h>
-#include "vlv_sideband_reg.h"
+#include "vlv_iosf_sb_reg.h"
enum pipe;
struct drm_i915_private;
{
}
-#endif /* _VLV_SIDEBAND_H_ */
+#endif /* _VLV_IOSF_SB_H_ */
* Copyright © 2023 Intel Corporation
*/
-#include "../../i915/vlv_sideband_reg.h"
+#include "../../i915/vlv_iosf_sb_reg.h"