arm64: dts: renesas: r9a09g057: Add CANFD node

Add CANFD node to RZ/V2H(P) ("R9A09G057") SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251224175204.3400062-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 77f986a957ba6ee53f0653b8130ad11aa7aac429..80cba9fcfe7bfa6f3f4c1f6592576485e4967a38 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -690,6 +690,66 @@
                        status = "disabled";
                };
 
+               canfd: can@12440000 {
+                       compatible = "renesas,r9a09g057-canfd", "renesas,r9a09g047-canfd";
+                       reg = <0 0x12440000 0 0x40000>;
+                       interrupts = <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 698 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "g_err", "g_recc",
+                                         "ch0_err", "ch0_rec", "ch0_trx",
+                                         "ch1_err", "ch1_rec", "ch1_trx",
+                                         "ch2_err", "ch2_rec", "ch2_trx",
+                                         "ch3_err", "ch3_rec", "ch3_trx",
+                                         "ch4_err", "ch4_rec", "ch4_trx",
+                                         "ch5_err", "ch5_rec", "ch5_trx";
+                       clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>,
+                                <&cpg CPG_MOD 0x9e>;
+                       clock-names = "fck", "ram_clk", "can_clk";
+                       assigned-clocks = <&cpg CPG_MOD 0x9e>;
+                       assigned-clock-rates = <80000000>;
+                       resets = <&cpg 0xa1>, <&cpg 0xa2>;
+                       reset-names = "rstp_n", "rstc_n";
+                       power-domains = <&cpg>;
+                       status = "disabled";
+
+                       channel0 {
+                               status = "disabled";
+                       };
+                       channel1 {
+                               status = "disabled";
+                       };
+                       channel2 {
+                               status = "disabled";
+                       };
+                       channel3 {
+                               status = "disabled";
+                       };
+                       channel4 {
+                               status = "disabled";
+                       };
+                       channel5 {
+                               status = "disabled";
+                       };
+               };
+
                rspi0: spi@12800000 {
                        compatible = "renesas,r9a09g057-rspi";
                        reg = <0x0 0x12800000 0x0 0x400>;