mtd: spi-nor: spansion: add support for S28HS02GT

Add support for S28HS02GT. Infineon S28HS02GT is a 2Gb,
multi-chip package, Octal SPI Flash.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Link: https://lore.kernel.org/r/20230726075257.12985-9-tudor.ambarus@linaro.org
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>

diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index d7aa0a90949ae9b695be98e32fe2abc3f5546b32..1c5671a3751a77a98bc8b5cd399cc67d4ad2c2a8 100644 (file)
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -693,22 +693,23 @@ static int cypress_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
 
 static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor)
 {
+       struct spi_nor_flash_parameter *params = nor->params;
        /*
         * On older versions of the flash the xSPI Profile 1.0 table has the
         * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE.
         */
-       if (nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0)
-               nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =
+       if (params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0)
+               params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =
                        SPINOR_OP_CYPRESS_RD_FAST;
 
        /* This flash is also missing the 4-byte Page Program opcode bit. */
-       spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP],
+       spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
                                SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
        /*
         * Since xSPI Page Program opcode is backward compatible with
         * Legacy SPI, use Legacy SPI opcode there as well.
         */
-       spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
+       spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
                                SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR);
 
        /*
@@ -716,7 +717,11 @@ static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor)
         * address bytes needed for Read Status Register command as 0 but the
         * actual value for that is 4.
         */
-       nor->params->rdsr_addr_nbytes = 4;
+       params->rdsr_addr_nbytes = 4;
+
+       /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */
+       if (params->size == SZ_256M)
+               params->n_dice = 2;
 
        return cypress_nor_get_page_size(nor);
 }
@@ -916,6 +921,11 @@ static const struct flash_info spansion_nor_parts[] = {
                MFR_FLAGS(USE_CLPEF)
                .fixups = &s28hx_t_fixups,
        },
+       { "s28hs02gt",   INFO(0x345b1c,      0, 0, 0)
+               PARSE_SFDP
+               MFR_FLAGS(USE_CLPEF)
+               .fixups = &s28hx_t_fixups,
+       },
 };
 
 /**