drm/xe: Translate C-state "reset value" into RC6

There are higher level sleep states that will cause RC6 state readout to
come back with an "in-reset" value. That is the case with NVL-P. As
those states are only possible if the GT is already in C6, let's just
translate the "reset value" into C6 when doing the readout.

Bspec: 67651
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20260309-extra-nvl-p-enabling-patches-v5-7-be9c902ee34e@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 7b927862f00349a520f68b4297b59cf224fe3a1b..84b80e83ac460b0af3777741ef02b15da707a4a6 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -20,6 +20,7 @@
 #define MTL_MIRROR_TARGET_WP1                          XE_REG(0xc60)
 #define   MTL_CAGF_MASK                                        REG_GENMASK(8, 0)
 #define   MTL_CC_MASK                                  REG_GENMASK(12, 9)
+#define   MTL_CRST                                     0xf
 
 /* RPM unit config (Gen8+) */
 #define RPM_CONFIG0                                    XE_REG(0xd00)

diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index 21fe73ab4583e88ddb0f4f72a467a22cda12a988..bb8c4e7934926df166fd1109006ea47ac592f14f 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -756,6 +756,14 @@ enum xe_gt_idle_state xe_guc_pc_c_status(struct xe_guc_pc *pc)
        if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
                reg = xe_mmio_read32(&gt->mmio, MTL_MIRROR_TARGET_WP1);
                gt_c_state = REG_FIELD_GET(MTL_CC_MASK, reg);
+
+               /*
+                * There are higher level sleep states that will cause this
+                * field to read out as its reset state, and those are only
+                * possible after the GT is already in C6.
+                */
+               if (gt_c_state == MTL_CRST)
+                       gt_c_state = GT_C6;
        } else {
                reg = xe_mmio_read32(&gt->mmio, GT_CORE_STATUS);
                gt_c_state = REG_FIELD_GET(RCN_MASK, reg);