]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
net: stmmac: add BASE-X support to integrated PCS
authorRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Wed, 18 Mar 2026 16:06:26 +0000 (16:06 +0000)
committerJakub Kicinski <kuba@kernel.org>
Tue, 24 Mar 2026 00:32:19 +0000 (17:32 -0700)
The integrated PCS supports 802.3z (BASE-X) modes when the Synopsys
IP is coupled with an appropriate SerDes to provide the electrical
interface. The PCS presents a TBI interface to the SerDes for this.
Thus, the BASE-X related registers are only present when TBI mode is
supported.

dwmac-qcom-ethqos added support for using 2.5G with the integrated PCS
by calling dwmac_ctrl_ane() directly.

Add support for the following to the integrated PCS:
- 1000BASE-X protocol unconditionally.
- 2500BASE-X if the coupled SerDes supports 2.5G speed.
- The above without autonegotiation.
- If the PCS supports TBI, then optional BASE-X autonegotiation for each
  of the above.

Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1w2tPe-0000000DYAp-1qpV@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
include/linux/stmmac.h

index df72f7c5a6a7b6fa0b87881e829a8aa006f237d9..df37af5ab837afadfb4430929aedabd4454b68a7 100644 (file)
 #define GMAC_RGSMII_SPEED_2_5          0
 #define GMAC_RGSMII_LNKSTS             BIT(3)
 
+static unsigned int dwmac_integrated_pcs_inband_caps(struct phylink_pcs *pcs,
+                                                    phy_interface_t interface)
+{
+       struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
+       unsigned int ib_caps;
+
+       if (phy_interface_mode_is_8023z(interface)) {
+               ib_caps = LINK_INBAND_DISABLE;
+
+               /* If the PCS supports TBI/RTBI, then BASE-X negotiation is
+                * supported.
+                */
+               if (spcs->support_tbi_rtbi)
+                       ib_caps |= LINK_INBAND_ENABLE;
+
+               return ib_caps;
+       }
+
+       return 0;
+}
+
 static int dwmac_integrated_pcs_enable(struct phylink_pcs *pcs)
 {
        struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
@@ -47,12 +68,20 @@ static void dwmac_integrated_pcs_get_state(struct phylink_pcs *pcs,
                                           struct phylink_link_state *state)
 {
        struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
-       u32 status, rgsmii;
+       u32 status, lpa, rgsmii;
 
        status = readl(spcs->base + GMAC_AN_STATUS);
 
        if (phy_interface_mode_is_8023z(state->interface)) {
-               state->link = false;
+               /* For BASE-X modes, the PCS block supports the advertisement
+                * and link partner advertisement registers using standard
+                * 802.3 format. The status register also has the link status
+                * and AN complete bits in the same bit location. This will
+                * only be used when AN is enabled.
+                */
+               lpa = readl(spcs->base + GMAC_ANE_LPA);
+
+               phylink_mii_c22_pcs_decode_state(state, neg_mode, status, lpa);
        } else {
                rgsmii = field_get(spcs->rgsmii_status_mask,
                                   readl(spcs->rgsmii));
@@ -84,6 +113,21 @@ static void dwmac_integrated_pcs_get_state(struct phylink_pcs *pcs,
        }
 }
 
+static int dwmac_integrated_pcs_config_aneg(struct stmmac_pcs *spcs,
+                                           phy_interface_t interface,
+                                           const unsigned long *advertising)
+{
+       bool changed = false;
+       u32 adv;
+
+       adv = phylink_mii_c22_pcs_encode_advertisement(interface, advertising);
+       if (readl(spcs->base + GMAC_ANE_ADV) != adv)
+               changed = true;
+       writel(adv, spcs->base + GMAC_ANE_ADV);
+
+       return changed;
+}
+
 static int dwmac_integrated_pcs_config(struct phylink_pcs *pcs,
                                       unsigned int neg_mode,
                                       phy_interface_t interface,
@@ -91,17 +135,46 @@ static int dwmac_integrated_pcs_config(struct phylink_pcs *pcs,
                                       bool permit_pause_to_mac)
 {
        struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
+       bool changed = false, ane = true;
+
+       /* Only configure the advertisement and allow AN in BASE-X mode if
+        * the core supports TBI/RTBI. AN will be filtered out by via phylink
+        * and the .pcs_inband_caps() method above.
+        */
+       if (phy_interface_mode_is_8023z(interface) &&
+           spcs->support_tbi_rtbi) {
+               ane = neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED;
+
+               changed = dwmac_integrated_pcs_config_aneg(spcs, interface,
+                                                          advertising);
+       }
 
-       dwmac_ctrl_ane(spcs->base, 0, 1, spcs->priv->hw->reverse_sgmii_enable);
+       dwmac_ctrl_ane(spcs->base, 0, ane,
+                      spcs->priv->hw->reverse_sgmii_enable);
 
-       return 0;
+       return changed;
+}
+
+static void dwmac_integrated_pcs_an_restart(struct phylink_pcs *pcs)
+{
+       struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
+       void __iomem *an_control = spcs->base + GMAC_AN_CTRL(0);
+       u32 ctrl;
+
+       /* We can only do AN restart if using TBI/RTBI mode */
+       if (spcs->support_tbi_rtbi) {
+               ctrl = readl(an_control) | GMAC_AN_CTRL_RAN;
+               writel(ctrl, an_control);
+       }
 }
 
 static const struct phylink_pcs_ops dwmac_integrated_pcs_ops = {
+       .pcs_inband_caps = dwmac_integrated_pcs_inband_caps,
        .pcs_enable = dwmac_integrated_pcs_enable,
        .pcs_disable = dwmac_integrated_pcs_disable,
        .pcs_get_state = dwmac_integrated_pcs_get_state,
        .pcs_config = dwmac_integrated_pcs_config,
+       .pcs_an_restart = dwmac_integrated_pcs_an_restart,
 };
 
 void stmmac_integrated_pcs_irq(struct stmmac_priv *priv, u32 status,
@@ -129,9 +202,18 @@ void stmmac_integrated_pcs_irq(struct stmmac_priv *priv, u32 status,
 int stmmac_integrated_pcs_get_phy_intf_sel(struct phylink_pcs *pcs,
                                           phy_interface_t interface)
 {
+       struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
+
        if (interface == PHY_INTERFACE_MODE_SGMII)
                return PHY_INTF_SEL_SGMII;
 
+       if (phy_interface_mode_is_8023z(interface)) {
+               if (spcs->support_tbi_rtbi)
+                       return PHY_INTF_SEL_TBI;
+               else
+                       return PHY_INTF_SEL_SGMII;
+       }
+
        return -EINVAL;
 }
 
@@ -151,7 +233,20 @@ int stmmac_integrated_pcs_init(struct stmmac_priv *priv,
        spcs->int_mask = pcs_info->int_mask;
        spcs->pcs.ops = &dwmac_integrated_pcs_ops;
 
+       /* If the PCS supports extended status, then it supports BASE-X AN
+        * with a TBI interface to the SerDes. Otherwise, we can support
+        * BASE-X without AN using SGMII, which is required for qcom-ethqos.
+        */
+       if (readl(spcs->base + GMAC_AN_STATUS) & BMSR_ESTATEN)
+               spcs->support_tbi_rtbi = true;
+
        __set_bit(PHY_INTERFACE_MODE_SGMII, spcs->pcs.supported_interfaces);
+       __set_bit(PHY_INTERFACE_MODE_1000BASEX, spcs->pcs.supported_interfaces);
+
+       /* Only allow 2500BASE-X if the SerDes has support. */
+       if (priv->plat->flags & STMMAC_FLAG_SERDES_SUPPORTS_2500M)
+               __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+                         spcs->pcs.supported_interfaces);
 
        priv->integrated_pcs = spcs;
 
index 09e609f111b1b167b6c69ab0ff63ba15dbee45fc..b2b12d34b3dd1a71d1f82d46f8c37aee335bf370 100644 (file)
@@ -41,6 +41,7 @@ struct stmmac_pcs {
        u32 rgsmii_status_mask;
        u32 int_mask;
        struct phylink_pcs pcs;
+       bool support_tbi_rtbi;
 };
 
 static inline struct stmmac_pcs *
index 565bb394b19458b1d4883e35803c79ef706c4228..5b2bece81448dc4ca1a365171788bb3576cea284 100644 (file)
@@ -212,6 +212,7 @@ enum dwmac_core_type {
 #define STMMAC_FLAG_EN_TX_LPI_CLK_PHY_CAP      BIT(12)
 #define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY   BIT(13)
 #define STMMAC_FLAG_KEEP_PREAMBLE_BEFORE_SFD   BIT(14)
+#define STMMAC_FLAG_SERDES_SUPPORTS_2500M      BIT(15)
 
 struct mac_device_info;