+2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
+
+ * config/tc-aarch64.c (parse_perms): New function.
+ (parse_operands): Add PERM.
+ * testsuite/gas/aarch64/morello_insn-c64.d: Add tests.
+ * testsuite/gas/aarch64/morello_insn.d: Likewise.
+ * testsuite/gas/aarch64/morello_insn.s: Likewise.
+
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* testsuite/gas/aarch64/morello_insn-c64.d: Add tests.
return true;
}
+static bool
+parse_perms (char **str, aarch64_opnd_info *info)
+{
+ char *p = *str;
+ char c;
+ aarch64_insn perms = 0;
+
+ /* Numeric value of permissions. */
+ if (ISDIGIT (*p) || (*p == '#' && p++))
+ {
+ perms = *p - '0';
+ if (p[1] > 0 || perms > 7)
+ {
+ set_syntax_error (_("invalid permission value"));
+ return false;
+ }
+ p += 2;
+ goto out;
+ }
+
+ /* Permission specifier mnemonics r, w and x, in that order. Do not accept
+ jumbled up sequences such as rxw, wrx, etc. and also reject duplicate
+ permissions such as rrxw. */
+ while ((c = *p++) != '\0')
+ {
+ aarch64_insn i = get_perm_bit (c);
+ if (i > 7 || i & perms || (i - 1) & perms)
+ {
+ set_syntax_error (_("invalid permissions"));
+ return false;
+ }
+ perms |= i;
+ }
+
+out:
+ *str = p - 1;
+ info->perm = perms;
+ return true;
+}
+
/* Generic instruction operand parser. This does no encoding and no
semantic validation; it merely squirrels values away in the inst
structure. Returns TRUE or FALSE depending on whether the
}
break;
+ case AARCH64_OPND_PERM:
+ po_misc_or_fail (parse_perms (&str, info));
+ break;
+
case AARCH64_OPND_COND:
case AARCH64_OPND_COND1:
{
.*: c2c1d26b mov c11, c19
.*: c2c1d26b mov c11, c19
.*: c2d38561 chkss c11, c19
+.*: c2c1926b clrtag c11, c19
.*: c2c1d3eb mov c11, csp
.*: c2c1d3eb mov c11, csp
.*: c2df8561 chkss c11, csp
+.*: c2c193eb clrtag c11, csp
.*: c2c1d17f mov csp, c11
.*: c2c1d17f mov csp, c11
.*: c2cb87e1 chkss csp, c11
+.*: c2c1917f clrtag csp, c11
.*: c2c1d3ff mov csp, csp
.*: c2c1d3ff mov csp, csp
.*: c2df87e1 chkss csp, csp
+.*: c2c193ff clrtag csp, csp
.*: aa1f03e0 mov x0, xzr
.*: c2c59020 cvtd c0, x1
.*: c2c5d020 cvtdz c0, x1
.*: c2cf5bff alignu csp, csp, #30
.*: c2c05bff alignu csp, csp, #0
.*: c2d05bff alignu csp, csp, #32
+.*: c2c692f6 clrperm c22, c23, r
+.*: c2c652f6 clrperm c22, c23, w
+.*: c2c632f6 clrperm c22, c23, x
+.*: c2c6b2f6 clrperm c22, c23, rx
+.*: c2c672f6 clrperm c22, c23, wx
+.*: c2c6d2f6 clrperm c22, c23, rw
+.*: c2c6f2f6 clrperm c22, c23, rwx
+.*: c2c612f6 clrperm c22, c23, #0
+.*: c2c632f6 clrperm c22, c23, x
+.*: c2c652f6 clrperm c22, c23, w
+.*: c2c672f6 clrperm c22, c23, wx
+.*: c2c692f6 clrperm c22, c23, r
+.*: c2c6b2f6 clrperm c22, c23, rx
+.*: c2c6d2f6 clrperm c22, c23, rw
+.*: c2c6f2f6 clrperm c22, c23, rwx
.*: c2d928c7 bicflgs c7, c6, x25
.*: c2d9a8c7 eorflgs c7, c6, x25
.*: c2d968c7 orrflgs c7, c6, x25
+.*: c2d9a0c7 clrperm c7, c6, x25
.*: c2d92be7 bicflgs c7, csp, x25
.*: c2d9abe7 eorflgs c7, csp, x25
.*: c2d96be7 orrflgs c7, csp, x25
+.*: c2d9a3e7 clrperm c7, csp, x25
.*: c2d928df bicflgs csp, c6, x25
.*: c2d9a8df eorflgs csp, c6, x25
.*: c2d968df orrflgs csp, c6, x25
+.*: c2d9a0df clrperm csp, c6, x25
.*: c2d92bff bicflgs csp, csp, x25
.*: c2d9abff eorflgs csp, csp, x25
.*: c2d96bff orrflgs csp, csp, x25
+.*: c2d9a3ff clrperm csp, csp, x25
.*: c2ee99a4 subs x4, c13, c14
.*: c2c4a440 blrs c29, c2, c4
.*: c2c48440 brs c29, c2, c4
.*: c2c1d26b mov c11, c19
.*: c2c1d26b mov c11, c19
.*: c2d38561 chkss c11, c19
+.*: c2c1926b clrtag c11, c19
.*: c2c1d3eb mov c11, csp
.*: c2c1d3eb mov c11, csp
.*: c2df8561 chkss c11, csp
+.*: c2c193eb clrtag c11, csp
.*: c2c1d17f mov csp, c11
.*: c2c1d17f mov csp, c11
.*: c2cb87e1 chkss csp, c11
+.*: c2c1917f clrtag csp, c11
.*: c2c1d3ff mov csp, csp
.*: c2c1d3ff mov csp, csp
.*: c2df87e1 chkss csp, csp
+.*: c2c193ff clrtag csp, csp
.*: aa1f03e0 mov x0, xzr
.*: c2c59020 cvtd c0, x1
.*: c2c5d020 cvtdz c0, x1
.*: c2cf5bff alignu csp, csp, #30
.*: c2c05bff alignu csp, csp, #0
.*: c2d05bff alignu csp, csp, #32
+.*: c2c692f6 clrperm c22, c23, r
+.*: c2c652f6 clrperm c22, c23, w
+.*: c2c632f6 clrperm c22, c23, x
+.*: c2c6b2f6 clrperm c22, c23, rx
+.*: c2c672f6 clrperm c22, c23, wx
+.*: c2c6d2f6 clrperm c22, c23, rw
+.*: c2c6f2f6 clrperm c22, c23, rwx
+.*: c2c612f6 clrperm c22, c23, #0
+.*: c2c632f6 clrperm c22, c23, x
+.*: c2c652f6 clrperm c22, c23, w
+.*: c2c672f6 clrperm c22, c23, wx
+.*: c2c692f6 clrperm c22, c23, r
+.*: c2c6b2f6 clrperm c22, c23, rx
+.*: c2c6d2f6 clrperm c22, c23, rw
+.*: c2c6f2f6 clrperm c22, c23, rwx
.*: c2d928c7 bicflgs c7, c6, x25
.*: c2d9a8c7 eorflgs c7, c6, x25
.*: c2d968c7 orrflgs c7, c6, x25
+.*: c2d9a0c7 clrperm c7, c6, x25
.*: c2d92be7 bicflgs c7, csp, x25
.*: c2d9abe7 eorflgs c7, csp, x25
.*: c2d96be7 orrflgs c7, csp, x25
+.*: c2d9a3e7 clrperm c7, csp, x25
.*: c2d928df bicflgs csp, c6, x25
.*: c2d9a8df eorflgs csp, c6, x25
.*: c2d968df orrflgs csp, c6, x25
+.*: c2d9a0df clrperm csp, c6, x25
.*: c2d92bff bicflgs csp, csp, x25
.*: c2d9abff eorflgs csp, csp, x25
.*: c2d96bff orrflgs csp, csp, x25
+.*: c2d9a3ff clrperm csp, csp, x25
.*: c2ee99a4 subs x4, c13, c14
.*: c2c4a440 blrs c29, c2, c4
.*: c2c48440 brs c29, c2, c4
// Two operands (dn).
.macro morello_cspcsp cdsp, cnsp
- .irp op, cpy, mov, chkss
+ .irp op, cpy, mov, chkss, clrtag
\op \cdsp, \cnsp
.endr
.endm
morello_cspcspi6 c18, csp
morello_cspcspi6 csp, csp
+ .macro morello_perm cd, cn
+ .irp perm, r, w, x, rx, wx, rw, rwx, #0, #1, #2, #3, #4, #5, #6, #7
+ clrperm \cd, \cn, \perm
+ .endr
+ .endm
+morello_perm c22, c23
+
// Three operands (dnm)
.macro morello_cspcspx cdsp, cnsp, xm
- .irp op, bicflgs, eorflgs, orrflgs
+ .irp op, bicflgs, eorflgs, orrflgs, clrperm
\op \cdsp, \cnsp, \xm
.endr
.endm
+2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
+
+ * opcode/aarch64.h (aarch64_operand_class): Add PERM.
+ (aarch64_opnd): Add PERM.
+ (get_perm_bit): New function.
+ (aarch64_opnd_info): New member perm.
+
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add CST_REG, Cam_SP
AARCH64_OPND_CLASS_SYSTEM,
AARCH64_OPND_CLASS_COND,
AARCH64_OPND_CLASS_CAP_REG,
+ AARCH64_OPND_CLASS_PERM,
};
/* Operand code that helps both parsing and coding.
BRS/BLRS. */
AARCH64_OPND_A64C_AIMM, /* Add immediate for A64C ADD/SUB. */
AARCH64_OPND_A64C_IMM8, /* IMM8 for BICFLGS. */
+ AARCH64_OPND_PERM, /* 3-bit capability permission for e.g. CLRPERM. */
};
/* Qualifier constrains an operand. It either specifies a variant of an
const aarch64_cond* get_cond_from_value (aarch64_insn value);
const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
+
+/* Capability permissions. */
+aarch64_insn get_perm_bit (const char p);
\f
/* Structure representing an operand. */
} za_tile_vector;
const aarch64_cond *cond;
+ aarch64_insn perm;
/* The encoding of the PSTATE field. */
aarch64_insn pstatefield;
const aarch64_sys_ins_reg *sysins_op;
+2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
+
+ * aarch64-asm.c (aarch64_ins_perm): New function.
+ * aarch64-asm.h (ins_perm): New function.
+ * aarch64-dis.c (aarch64_ext_perm): New function.
+ * aarch64-dis.h (ext_perm): New function.
+ * aarch64-opc.c (fields): New field perm.
+ (get_perm_str, get_perm_bit): New functions.
+ (aarch64_print_operand): Add PERM.
+ * aarch64-opc.h (aarch64_field_kind): Add perm.
+ * aarch64-tbl.h (QL_I2SAMEQ): New macro.
+ (aarch64_opcode_table): New instructions.
+ (AARCH64_OPERANDS): New operands.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+
2020-10-20 Siddhesh Poyarekar <siddesh.poyarekar@arm.com>
* aarch64-tbl.h (QL2_A64C_X_CA, QL2_A64C_CA_X, QL2_A64C_X_X,
return true;
}
+/* Encode the permission operand for e.g. CLRPERM, <Cd>, <Cn>, <perm>. */
+bool
+aarch64_ins_perm (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ /* perm */
+ insert_field (FLD_perm, code, info->perm, 0);
+ return true;
+}
+
/* Encode the system register operand for e.g. MRS <Xt>, <systemreg>. */
bool
aarch64_ins_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
AARCH64_DECL_OPD_INSERTER (ins_addr_uimm12);
AARCH64_DECL_OPD_INSERTER (ins_simd_addr_post);
AARCH64_DECL_OPD_INSERTER (ins_cond);
+AARCH64_DECL_OPD_INSERTER (ins_perm);
AARCH64_DECL_OPD_INSERTER (ins_sysreg);
AARCH64_DECL_OPD_INSERTER (ins_pstatefield);
AARCH64_DECL_OPD_INSERTER (ins_sysins_op);
return true;
}
+/* Decode the permission operand for e.g. CLRPERM <Cd>, <Cn>, <perm>. */
+bool
+aarch64_ext_perm (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ aarch64_opnd_info *info,
+ aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ /* perm */
+ info->perm = extract_field (FLD_perm, code, 0);
+ return true;
+}
+
/* Decode the system register operand for e.g. MRS <Xt>, <systemreg>. */
bool
aarch64_ext_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_uimm12);
AARCH64_DECL_OPD_EXTRACTOR (ext_simd_addr_post);
AARCH64_DECL_OPD_EXTRACTOR (ext_cond);
+AARCH64_DECL_OPD_EXTRACTOR (ext_perm);
AARCH64_DECL_OPD_EXTRACTOR (ext_sysreg);
AARCH64_DECL_OPD_EXTRACTOR (ext_pstatefield);
AARCH64_DECL_OPD_EXTRACTOR (ext_sysins_op);
type instructions. */
{ 22, 1 }, /* a64c_shift_ai: Shift bit in immediate ADD/SUB. */
{ 13, 8 }, /* a64c_imm8: BICFLGS imm8. */
+ { 13, 3 }, /* perm: permission specifier in clrperm. */
};
enum aarch64_operand_class
return &aarch64_conds[cond->value ^ 0x1];
}
+/* Return a permission string in OUT. OUT needs to be at least 4 bytes wide. */
+static void
+get_perm_str (aarch64_insn perm, char *out)
+{
+ int i = 0;
+ assert (perm < 8);
+
+ /* XXX 0x0 is a valid permission, i.e. no permissions at all. The
+ reference however deems the value to be RESERVED. */
+ if (perm == 0)
+ {
+ out[i++] = '#';
+ out[i++] = '0';
+ }
+
+ if (perm & 4)
+ out[i++] = 'r';
+ if (perm & 2)
+ out[i++] = 'w';
+ if (perm & 1)
+ out[i++] = 'x';
+
+ out [i] = '\0';
+}
+
+aarch64_insn
+get_perm_bit (char p)
+{
+ switch (p)
+ {
+ case 'r':
+ return 4;
+ case 'w':
+ return 2;
+ case 'x':
+ return 1;
+ }
+
+ return 8;
+}
+
/* Table describing the operand extension/shifting operators; indexed by
enum aarch64_modifier_kind.
snprintf (buf, size, "#0x%x", (unsigned int)opnd->imm.value);
break;
+ case AARCH64_OPND_PERM:
+ {
+ char perm[4];
+ get_perm_str (opnd->perm, perm);
+ snprintf (buf, size, "%s", perm);
+ }
+ break;
+
case AARCH64_OPND_COND:
case AARCH64_OPND_COND1:
snprintf (buf, size, "%s", opnd->cond->names[0]);
FLD_Cat2,
FLD_a64c_shift_ai,
FLD_a64c_imm8,
+ FLD_perm,
};
/* Field description. */
QLF2(X,X), \
}
+#define QL_I2SAMEQ \
+{ \
+ QLF2(S_Q,S_Q), \
+}
+
/* e.g. CRC32B <Wd>, <Wn>, <Wm>. */
#define QL_I3SAMEW \
{ \
A64C_INSN ("chksld", 0xc2c21001, 0xfffffc1f, a64c, 0, OP1 (Can_SP), QL1_A64C_CA, 0),
A64C_INSN ("chktgd", 0xc2c23001, 0xfffffc1f, a64c, 0, OP1 (Can_SP), QL1_A64C_CA, 0),
A64C_INSN ("chkssu", 0xc2c08800, 0xffe0fc00, a64c, 0, OP3 (Cad, Can_SP, Cam_SP), QL3_A64C_CA_CA_CA, 0),
+ A64C_INSN ("clrtag", 0xc2c19000, 0xfffffc00, a64c, 0, OP2 (Cad_SP, Can_SP), QL2_A64C_CA_CA, 0),
+ A64C_INSN ("clrperm", 0xc2c0a000, 0xffe0fc00, a64c, 0, OP3 (Cad_SP, Can_SP, Rm), QL3_A64C_CA_CA_X, 0),
+ A64C_INSN ("clrperm", 0xc2c61000, 0xffff1c00, a64c, 0, OP3 (Cad_SP, Can_SP, PERM), QL3_A64C_CA_CA_X, 0),
A64C_INSN ("cseal", 0xc2c04400, 0xffe0fc00, a64c, 0, OP3 (Cad_SP, Can_SP, Cam_SP), QL3_A64C_CA_CA_CA, 0),
A64C_INSN ("csel", 0xc2c00c00, 0xffe00c00, a64c, 0, OP4 (Cad, Can, Cam, COND), QL4_A64C_CSEL, 0),
A64C_INSN ("cthi", 0xc2c0e800, 0xffe0fc00, a64c, 0, OP3 (Cad_SP, Can, Rm), QL3_A64C_CA_CA_X, 0),
F(FLD_a64c_shift_ai,FLD_imm12), \
"a 12-bit unsigned immediate with optional left shift of 12 bits")\
Y(IMMEDIATE, imm, "A64C_IMM8", 0, F(FLD_a64c_imm8), \
- "8-bit unsigned immediate")
+ "8-bit unsigned immediate") \
+ Y(PERM, perm, "PERM", 0, F(), "a capability permission")
projects / thirdparty / binutils-gdb.git / commitdiff
