arm64: dts: qcom: monaco: Add power-domain and iface clk for ice node

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for its own resources. Before accessing ICE hardware during probe, to
avoid potential unclocked register access issues (when clk_ignore_unused
is not passed on the kernel command line), in addition to the 'core' clock
the 'iface' clock should also be turned on by the driver. This can only be
done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the
GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for
monaco.

Fixes: cc9d29aad876d ("arm64: dts: qcom: qcs8300: enable the inline crypto engine")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-5-5ccf5d7e2846@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index ce6ff259cb4a012a2f4dfe666e91526cbc770f30..2660c161c3d74f4002aebff40634509e885fb3b3 100644 (file)
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -2737,7 +2737,11 @@
                        compatible = "qcom,qcs8300-inline-crypto-engine",
                                     "qcom,inline-crypto-engine";
                        reg = <0x0 0x01d88000 0x0 0x18000>;
-                       clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+                       clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+                                <&gcc GCC_UFS_PHY_AHB_CLK>;
+                       clock-names = "core",
+                                     "iface";
+                       power-domains = <&gcc GCC_UFS_PHY_GDSC>;
                };
 
                crypto: crypto@1dfa000 {