arm64: dts: imx8mp-skov: use I2C5 for DDC

The HDMI DDC pads can be muxed either to an i.MX I2C controller or
to a limited I2C controller within the Designware HDMI bridge.

So far, the pads were muxed to the HDMI bridge, but the i.MX I2C controller
is the better choice:

  - The Designware HDMI I2C controller doesn't support multi-byte
    requests and the Linux driver refuses[1] transfers to/from address
    0x37, but these are required for display/brightness configuration,

  - The driver doesn't support I2C bus recovery, but some HDMI panels used
    with the board can be flaky and require it.

As the i.MX I2C controller and driver don't have either of these
limitations, let's make use of it instead.

[1]: https://lore.kernel.org/all/20190722181945.244395-1-mka@chromium.org/

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts
index c1ca69da3cb8edf5424b727e3ba8bb74affe8e93..206116be816662349ef5b54e288b945f171f5637 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts
@@ -9,12 +9,34 @@
        compatible = "skov,imx8mp-skov-revb-hdmi", "fsl,imx8mp";
 };
 
+&i2c5 {
+       pinctrl-names = "default", "gpio";
+       pinctrl-0 = <&pinctrl_i2c5>;
+       pinctrl-1 = <&pinctrl_i2c5_gpio>;
+       scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+       sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+       clock-frequency = <100000>;
+       status = "okay";
+};
+
 &iomuxc {
        pinctrl_hdmi: hdmigrp {
                fsl,pins = <
-                       MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL             0x1c3
-                       MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA             0x1c3
                        MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD                 0x19
                >;
        };
+
+       pinctrl_i2c5: i2c5grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL                     0x400001c2
+                       MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA                     0x400001c2
+               >;
+       };
+
+       pinctrl_i2c5_gpio: i2c5gpiogrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26                   0x400001c2
+                       MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27                   0x400001c2
+               >;
+       };
 };