drm/amdgpu: Rename KGD_MAX_QUEUES to AMDGPU_MAX_QUEUES

Rename KGD_MAX_QUEUES to AMDGPU_MAX_QUEUES to conform with
the naming convention followed in amdgpu_gfx.h. No functional
change.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 25d5fda5b243e3c598c141952f9537fe3c9652d7..26ff5f8d97957cace95309ae330632d3ebd02aab 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -164,7 +164,7 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
                 */
                bitmap_complement(gpu_resources.cp_queue_bitmap,
                                  adev->gfx.mec_bitmap[0].queue_bitmap,
-                                 KGD_MAX_QUEUES);
+                                 AMDGPU_MAX_QUEUES);
 
                /* According to linux/bitmap.h we shouldn't use bitmap_clear if
                 * nbits is not compile time constant
@@ -172,7 +172,7 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
                last_valid_bit = 1 /* only first MEC can have compute queues */
                                * adev->gfx.mec.num_pipe_per_mec
                                * adev->gfx.mec.num_queue_per_pipe;
-               for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
+               for (i = last_valid_bit; i < AMDGPU_MAX_QUEUES; ++i)
                        clear_bit(i, gpu_resources.cp_queue_bitmap);
 
                amdgpu_doorbell_get_kfd_info(adev,

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index 3c45a188b701ab0c406481146ff1942576acc413..04b8c7dacd309615f3a01be65abdd3ce00a26919 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -1037,7 +1037,7 @@ void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid,
        int pasid_tmp;
        int max_queue_cnt;
        int vmid_wave_cnt = 0;
-       DECLARE_BITMAP(cp_queue_bitmap, KGD_MAX_QUEUES);
+       DECLARE_BITMAP(cp_queue_bitmap, AMDGPU_MAX_QUEUES);
 
        lock_spi_csq_mutexes(adev);
        soc15_grbm_select(adev, 1, 0, 0, 0, inst);
@@ -1047,7 +1047,7 @@ void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid,
         * to get number of waves in flight
         */
        bitmap_complement(cp_queue_bitmap, adev->gfx.mec_bitmap[0].queue_bitmap,
-                         KGD_MAX_QUEUES);
+                         AMDGPU_MAX_QUEUES);
        max_queue_cnt = adev->gfx.mec.num_pipe_per_mec *
                        adev->gfx.mec.num_queue_per_pipe;
        sh_cnt = adev->gfx.config.max_sh_per_se;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 0ca95c4d4bfbe1634b270ac5afe04aec57636347..42ac6d1bf9cafd562d1331e5ffdc915fcce041e6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -43,10 +43,10 @@
 #define AMDGPU_GFX_LBPW_DISABLED_MODE          0x00000008L
 
 #define AMDGPU_MAX_GC_INSTANCES                8
-#define KGD_MAX_QUEUES                 128
+#define AMDGPU_MAX_QUEUES              128
 
-#define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
-#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
+#define AMDGPU_MAX_GFX_QUEUES AMDGPU_MAX_QUEUES
+#define AMDGPU_MAX_COMPUTE_QUEUES AMDGPU_MAX_QUEUES
 
 enum amdgpu_gfx_pipe_priority {
        AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1,

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 4170e3d32630ab0153c138f067a243b31e9cc7ed..6d07a5dd26489943b5ee3a226e0f79a8bc0f96b8 100644 (file)
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -92,7 +92,7 @@ static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)
 unsigned int get_cp_queues_num(struct device_queue_manager *dqm)
 {
        return bitmap_weight(dqm->dev->kfd->shared_resources.cp_queue_bitmap,
-                               KGD_MAX_QUEUES);
+                               AMDGPU_MAX_QUEUES);
 }
 
 unsigned int get_queues_per_pipe(struct device_queue_manager *dqm)
@@ -1576,7 +1576,7 @@ static int set_sched_resources(struct device_queue_manager *dqm)
        res.vmid_mask = dqm->dev->compute_vmid_bitmap;
 
        res.queue_mask = 0;
-       for (i = 0; i < KGD_MAX_QUEUES; ++i) {
+       for (i = 0; i < AMDGPU_MAX_QUEUES; ++i) {
                mec = (i / dqm->dev->kfd->shared_resources.num_queue_per_pipe)
                        / dqm->dev->kfd->shared_resources.num_pipe_per_mec;
 

diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
index 3b5a56585c4b7283017651aad21ed1c0565ad37f..255adc30f802cb83810fd701a1fd4394ca99b236 100644 (file)
--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
@@ -123,7 +123,7 @@ struct kgd2kfd_shared_resources {
        uint32_t num_queue_per_pipe;
 
        /* Bit n == 1 means Queue n is available for KFD */
-       DECLARE_BITMAP(cp_queue_bitmap, KGD_MAX_QUEUES);
+       DECLARE_BITMAP(cp_queue_bitmap, AMDGPU_MAX_QUEUES);
 
        /* SDMA doorbell assignments (SOC15 and later chips only). Only
         * specific doorbells are routed to each SDMA engine. Others