clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1} clocks

Add support for the PLLDSI{0,1} clocks in the r9a09g047 CPG driver.

Introduce CLK_PLLDSI{0,1} also, introduce the
rzg3e_cpg_pll_dsi{0,1}_limits structures to describe the frequency
constraints specific to the RZ/G3E SoC.

On Renesas RZ/G3E:

 - PLLDSI0 maximum output frequency: 1218 MHz
 - PLLDSI1 maximum output frequency: 609 MHz

These limits are enforced through the newly added
RZG3E_CPG_PLL_DSI{0,1}_LIMITS().

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://patch.msgid.link/d26ec5349b0eb7ddb7d244fc53d1111a8530328f.1775636898.git.tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 41464a6e9b5db4ff9a914862bb5a1cf597baf4c9..87d5924f7e79bb4a83464601e125a7dfc3421e0c 100644 (file)
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -6,6 +6,7 @@
  */
 
 #include <linux/clk-provider.h>
+#include <linux/clk/renesas.h>
 #include <linux/device.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -30,6 +31,8 @@ enum clk_ids {
        CLK_PLLCA55,
        CLK_PLLVDO,
        CLK_PLLETH,
+       CLK_PLLDSI0,
+       CLK_PLLDSI1,
 
        /* Internal Core Clocks */
        CLK_PLLCM33_DIV3,
@@ -117,6 +120,12 @@ static const struct clk_div_table dtable_16_128[] = {
        {0, 0},
 };
 
+RZG3E_CPG_PLL_DSI0_LIMITS(rzg3e_cpg_pll_dsi0_limits);
+RZG3E_CPG_PLL_DSI1_LIMITS(rzg3e_cpg_pll_dsi1_limits);
+
+#define PLLDSI0                PLL_PACK_LIMITS(0xc0, 1, 0, &rzg3e_cpg_pll_dsi0_limits)
+#define PLLDSI1                PLL_PACK_LIMITS(0x160, 1, 1, &rzg3e_cpg_pll_dsi1_limits)
+
 /* Mux clock tables */
 static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
 static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
@@ -138,6 +147,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
        DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
        DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
        DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
+       DEF_PLLDSI(".plldsi0", CLK_PLLDSI0, CLK_QEXTAL, PLLDSI0),
+       DEF_PLLDSI(".plldsi1", CLK_PLLDSI1, CLK_QEXTAL, PLLDSI1),
 
        /* Internal Core Clocks */
        DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),

diff --git a/include/linux/clk/renesas.h b/include/linux/clk/renesas.h
index c360df9fa735c66b9587be423e682e16b3efb38c..0949400f44de4007bde98b4f1e7efca1ab9e2d04 100644 (file)
--- a/include/linux/clk/renesas.h
+++ b/include/linux/clk/renesas.h
@@ -164,6 +164,26 @@ struct rzv2h_pll_div_pars {
                .k = { .min = -32768, .max = 32767 },                   \
        }                                                               \
 
+#define RZG3E_CPG_PLL_DSI0_LIMITS(name)                                        \
+       static const struct rzv2h_pll_limits (name) = {                 \
+               .fout = { .min = 25 * MEGA, .max = 1218 * MEGA },       \
+               .fvco = { .min = 1600 * MEGA, .max = 3200 * MEGA },     \
+               .m = { .min = 64, .max = 533 },                         \
+               .p = { .min = 1, .max = 4 },                            \
+               .s = { .min = 0, .max = 6 },                            \
+               .k = { .min = -32768, .max = 32767 },                   \
+       }                                                               \
+
+#define RZG3E_CPG_PLL_DSI1_LIMITS(name)                                        \
+       static const struct rzv2h_pll_limits (name) = {                 \
+               .fout = { .min = 25 * MEGA, .max = 609 * MEGA },        \
+               .fvco = { .min = 1600 * MEGA, .max = 3200 * MEGA },     \
+               .m = { .min = 64, .max = 533 },                         \
+               .p = { .min = 1, .max = 4 },                            \
+               .s = { .min = 0, .max = 6 },                            \
+               .k = { .min = -32768, .max = 32767 },                   \
+       }                                                               \
+
 #ifdef CONFIG_CLK_RZV2H
 bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits,
                        struct rzv2h_pll_pars *pars, u64 freq_millihz);