if (ret)
goto out;
+ ret = rtw89_chip_data_setup(rtwdev);
+ if (ret)
+ goto out;
+
rtw89_core_setup_rfe_parms(rtwdev);
rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev);
struct rtw89_debugfs;
struct rtw89_regd_data;
struct rtw89_wow_cam_info;
+struct rtw89_bb_wrap_data;
struct rtw89_fw_cmd_ofld_info;
extern const struct ieee80211_ops rtw89_ops;
enum rtw89_efuse_block block);
int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
void (*fem_setup)(struct rtw89_dev *rtwdev);
+ int (*data_setup)(struct rtw89_dev *rtwdev);
void (*rfe_gpio)(struct rtw89_dev *rtwdev);
void (*rfk_hw_init)(struct rtw89_dev *rtwdev);
void (*rfk_init)(struct rtw89_dev *rtwdev);
};
struct rtw89_phy_info {
+ const struct rtw89_bb_wrap_data *bb_wrap_data;
struct rtw89_bb_stat_cfg bb_stat_cfg;
};
chip->ops->fem_setup(rtwdev);
}
+static inline int rtw89_chip_data_setup(struct rtw89_dev *rtwdev)
+{
+ const struct rtw89_chip_info *chip = rtwdev->chip;
+
+ if (!chip->ops->data_setup)
+ return 0;
+
+ return chip->ops->data_setup(rtwdev);
+}
+
static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev)
{
const struct rtw89_chip_info *chip = rtwdev->chip;
const struct rtw89_fw_element_hdr *elm[RTW89_PHY_C2H_RFK_LOG_FUNC_NUM];
};
+struct rtw89_bb_wrap_data {
+};
+
struct rtw89_phy_gen_def {
u32 cr_base;
u32 physt_bmp_start;
.read_efuse = rtw8851b_read_efuse,
.read_phycap = rtw8851b_read_phycap,
.fem_setup = NULL,
+ .data_setup = NULL,
.rfe_gpio = rtw8851b_rfe_gpio,
.rfk_hw_init = NULL,
.rfk_init = rtw8851b_rfk_init,
.read_efuse = rtw8852a_read_efuse,
.read_phycap = rtw8852a_read_phycap,
.fem_setup = rtw8852a_fem_setup,
+ .data_setup = NULL,
.rfe_gpio = NULL,
.rfk_hw_init = NULL,
.rfk_init = rtw8852a_rfk_init,
.read_efuse = rtw8852bx_read_efuse,
.read_phycap = rtw8852bx_read_phycap,
.fem_setup = NULL,
+ .data_setup = NULL,
.rfe_gpio = NULL,
.rfk_hw_init = NULL,
.rfk_init = rtw8852b_rfk_init,
.read_efuse = rtw8852bx_read_efuse,
.read_phycap = rtw8852bx_read_phycap,
.fem_setup = NULL,
+ .data_setup = NULL,
.rfe_gpio = NULL,
.rfk_hw_init = NULL,
.rfk_init = rtw8852bt_rfk_init,
.read_efuse = rtw8852c_read_efuse,
.read_phycap = rtw8852c_read_phycap,
.fem_setup = NULL,
+ .data_setup = NULL,
.rfe_gpio = NULL,
.rfk_hw_init = NULL,
.rfk_init = rtw8852c_rfk_init,
.read_efuse = rtw8922a_read_efuse,
.read_phycap = rtw8922a_read_phycap,
.fem_setup = NULL,
+ .data_setup = NULL,
.rfe_gpio = NULL,
.rfk_hw_init = rtw8922a_rfk_hw_init,
.rfk_init = rtw8922a_rfk_init,
[RTW89_EFUSE_BLOCK_ADIE] = {.offset = 0x70000, .size = 0x10},
};
+static const struct rtw89_bb_wrap_data rtw8922d_bb_wrap_data_7025_default = {
+};
+
+static const struct rtw89_bb_wrap_data rtw8922d_bb_wrap_data_7090_default = {
+};
+
+static const struct rtw89_bb_wrap_data rtw8922d_bb_wrap_data_7090_rfe35_41_44 = {
+};
+
static void rtw8922d_sel_bt_rx_path(struct rtw89_dev *rtwdev, u8 val,
enum rtw89_rf_path rx_path)
{
rtw8922d_pad_bias_trim(rtwdev);
}
+static int rtw8922d_data_setup(struct rtw89_dev *rtwdev)
+{
+ const struct rtw89_bb_wrap_data *data;
+ struct rtw89_hal *hal = &rtwdev->hal;
+ bool rfe35_41_44 = false;
+
+ switch (rtwdev->efuse.rfe_type) {
+ case 35:
+ case 41:
+ case 44:
+ rfe35_41_44 = true;
+ break;
+ }
+
+ if (hal->cid == RTL8922D_CID7025) {
+ data = &rtw8922d_bb_wrap_data_7025_default;
+ } else {
+ if (rfe35_41_44)
+ data = &rtw8922d_bb_wrap_data_7090_rfe35_41_44;
+ else
+ data = &rtw8922d_bb_wrap_data_7090_default;
+ }
+
+ rtwdev->phy_info.bb_wrap_data = data;
+
+ return 0;
+}
+
static void rtw8922d_set_channel_mac(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan,
u8 mac_idx)
.read_efuse = rtw8922d_read_efuse,
.read_phycap = rtw8922d_read_phycap,
.fem_setup = NULL,
+ .data_setup = rtw8922d_data_setup,
.rfe_gpio = NULL,
.rfk_hw_init = rtw8922d_rfk_hw_init,
.rfk_init = rtw8922d_rfk_init,