arm64: dts: imx8m{m,n,p}-venice: disable unused clk output for TI PHY

Disable the unused refclk output for the TI DP83867 PHY used on
Gateworks Venice boards.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
index 37db4f0dd5052bb7e75d0bdc1f9f663ea2459575..baf46fe2813340c2b7038d9697ee62f30ae73b68 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
@@ -115,6 +115,7 @@
                ethphy0: ethernet-phy@0 {
                        compatible = "ethernet-phy-ieee802.3-c22";
                        reg = <0>;
+                       ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
                        ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
                        ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
                        tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
index c09b40fc6decd417e76b1afb008e7756b67e7116..468c7e993c52bc8fd9bc4ec09a05e7593df3e6b2 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
@@ -253,6 +253,7 @@
                ethphy0: ethernet-phy@0 {
                        compatible = "ethernet-phy-ieee802.3-c22";
                        reg = <0>;
+                       ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
                        ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
                        ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
                        tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts
index a5f52f60169e96052c37b040afd32d8c2e9f8234..5aa0e2cd155ec24e955f9d863d9d9318862e416e 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts
@@ -248,6 +248,7 @@
                ethphy0: ethernet-phy@0 {
                        compatible = "ethernet-phy-ieee802.3-c22";
                        reg = <0>;
+                       ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
                        ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
                        ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
                        tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi
index 303995a8adce8e3749a2e352e780cbfa2f5762f1..a1232a4f84853c9e72752e726f5a09374649a31c 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi
@@ -101,6 +101,7 @@
                        reg = <0x0>;
                        interrupt-parent = <&gpio3>;
                        interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+                       ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
                        ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
                        ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
                        tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
index 12de7cf1e8538e38df2ed6f2c8697d4f7597962a..7662663ff5dad8ea35e280784b9b17372e2348ca 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
@@ -228,6 +228,7 @@
                ethphy0: ethernet-phy@0 {
                        compatible = "ethernet-phy-ieee802.3-c22";
                        reg = <0x0>;
+                       ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
                        ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
                        ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
                        tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;