i386: Remove avx10.2-256 and avx10.2-512 options

When AVX10.2 options are added into GCC 15, E-core is supposed to
support up to 256 bit vector width, while P-core up to 512 bit vector
width. Therefore, we added avx10.2-256 and avx10.2-512 options into
compiler since there will be real platforms with 256 bit only support.

However, all the future platforms will now support 512 bit vector width,
including P-core and E-core. It will result in no need for split the
option for vector width. Therefore, we will remove them in this patch.

gcc/ChangeLog:

	* common/config/i386/cpuinfo.h
	(get_available_features): Revise the logic AVX10 version.
	* common/config/i386/i386-common.cc
	(OPTION_MASK_ISA2_AVX10_2_256_SET): Removed.
	(OPTION_MASK_ISA2_AVX10_2_512_SET): Ditto.
	(OPTION_MASK_ISA2_AVX10_2_SET): New.
	(OPTION_MASK_ISA2_AMX_AVX512_SET): Use AVX10.2 macro.
	(OPTION_MASK_ISA2_AVX10_2_UNSET): Ditto.
	(ix86_handle_option): Remove avx10.2-256 part. Adjust avx10.2.
	* common/config/i386/i386-cpuinfo.h
	(enum processor_features): Remove FEATURE_AVX10_2_256 and skip
	the value for it. Change the name from FEATURE_AVX10_2_512 to
	FEATURE_AVX10_2.
	* common/config/i386/i386-isas.h: Remove avx10.2-256/512.
	* config/i386/avx10_2-512bf16intrin.h: Use avx10.2 instead of
	avx10.2-256/512.
	* config/i386/avx10_2-512convertintrin.h: Ditto.
	* config/i386/avx10_2-512mediaintrin.h: Ditto.
	* config/i386/avx10_2-512minmaxintrin.h: Ditto.
	* config/i386/avx10_2-512satcvtintrin.h: Ditto.
	* config/i386/avx10_2bf16intrin.h: Ditto.
	* config/i386/avx10_2convertintrin.h: Ditto.
	* config/i386/avx10_2mediaintrin.h: Ditto.
	* config/i386/avx10_2minmaxintrin.h: Ditto.
	* config/i386/avx10_2satcvtintrin.h: Ditto.
	* config/i386/movrsintrin.h: Ditto.
	* config/i386/sm4intrin.h: Ditto.
	* config/i386/cpuid.h (bit_AVX10_256): Removed.
	(bit_AVX10_512): Ditto.
	* config/i386/driver-i386.cc (host_detect_local_cpu): Adjust
	Diamond Rapids and -march=native condition.
	* config/i386/i386-builtin.def (BDESC): Use AVX10.2 macro
	instead of AVX10.2-256/512.
	* config/i386/i386-c.cc (ix86_target_macros_internal): Ditto.
	* config/i386/i386-expand.cc
	(ix86_expand_branch): Use TARGET_AVX10_2 instead of specifying
	vector size.
	(ix86_prepare_fp_compare_args): Ditto.
	(ix86_expand_fp_compare): Ditto.
	(ix86_ssecom_setcc): Ditto.
	(ix86_expand_sse_comi): Ditto.
	(ix86_expand_sse_comi_round): Ditto.
	(ix86_check_builtin_isa_match): Ditto.
	* config/i386/i386.cc (ix86_fp_compare_code_to_integer): Ditto.
	(ix86_get_mask_mode): Ditto.
	* config/i386/i386.h (SSE_FLOAT_MODE_SSEMATH_OR_HFBF_P): Ditto.
	* config/i386/i386.md: Ditto.
	* config/i386/mmx.md: Ditto.
	* config/i386/sse.md: Ditto.
	* config/i386/predicates.md: Ditto.
	* config/i386/i386-isa.def (AVX10_2_256): Removed.
	(AVX10_2_512): Removed.
	(AVX10_2): New.
	* config/i386/i386-options.cc
	(isa2_opts): Remove avx10.2-256/512.
	(ix86_valid_target_attribute_inner_p): Ditto.
	(PTA_DIAMONDRAPIDS): Use PTA_AVX10_2.
	* config/i386/i386.opt: Remove avx10.2-256/512.
	* config/i386/i386.opt.urls: Ditto.
	* doc/extend.texi: Ditto.
	* doc/invoke.texi: Ditto.
	* doc/sourcebuild.texi: Ditto.

diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index a6ede14a3ccb9f5e5eaa8866e2f29c35d3234285..f8f288d17b84767bf79dcaea7bf6322b19759719 100644 (file)
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -1037,32 +1037,20 @@ get_available_features (struct __processor_model *cpu_model,
     {
       __cpuid_count (0x24, 0, eax, ebx, ecx, edx);
       version = ebx & 0xff;
-      if (ebx & bit_AVX10_256)
-       switch (version)
-         {
-         case 2:
-           set_feature (FEATURE_AVX10_2_256);
-           /* Fall through.  */
-         case 1:
-           set_feature (FEATURE_AVX10_1_256);
-           break;
-         default:
-           set_feature (FEATURE_AVX10_1_256);
-           break;
-         }
-      if (ebx & bit_AVX10_512)
-       switch (version)
-         {
-         case 2:
-           set_feature (FEATURE_AVX10_2_512);
-           /* Fall through.  */
-         case 1:
-           set_feature (FEATURE_AVX10_1_512);
-           break;
-         default:
-           set_feature (FEATURE_AVX10_1_512);
-           break;
-         }
+      switch (version)
+       {
+       case 2:
+         set_feature (FEATURE_AVX10_2);
+         /* Fall through.  */
+       case 1:
+         set_feature (FEATURE_AVX10_1_512);
+         set_feature (FEATURE_AVX10_1_256);
+         break;
+       default:
+         set_feature (FEATURE_AVX10_1_512);
+         set_feature (FEATURE_AVX10_1_256);
+         break;
+       }
     }
 
   /* Check cpuid level of extended features.  */

diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc
index 1788b5769cd4c2d86bed4b656ac342f6c9fa6392..df87bb4aaed319a01461e24efda58cdd35e24184 100644 (file)
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -122,13 +122,10 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA2_AVX10_1_256_SET OPTION_MASK_ISA2_AVX10_1_256
 #define OPTION_MASK_ISA2_AVX10_1_512_SET \
   (OPTION_MASK_ISA2_AVX10_1_256_SET | OPTION_MASK_ISA2_AVX10_1_512)
-#define OPTION_MASK_ISA2_AVX10_2_256_SET \
-  (OPTION_MASK_ISA2_AVX10_1_256_SET | OPTION_MASK_ISA2_AVX10_2_256)
-#define OPTION_MASK_ISA2_AVX10_2_512_SET \
-  (OPTION_MASK_ISA2_AVX10_1_512_SET | OPTION_MASK_ISA2_AVX10_2_256_SET \
-   | OPTION_MASK_ISA2_AVX10_2_512)
+#define OPTION_MASK_ISA2_AVX10_2_SET \
+  (OPTION_MASK_ISA2_AVX10_1_512_SET | OPTION_MASK_ISA2_AVX10_2)
 #define OPTION_MASK_ISA2_AMX_AVX512_SET \
-  (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AVX10_2_512_SET \
+  (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AVX10_2_SET \
    | OPTION_MASK_ISA2_AMX_AVX512)
 #define OPTION_MASK_ISA2_AMX_TF32_SET \
   (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_TF32)
@@ -329,8 +326,7 @@ along with GCC; see the file COPYING3.  If not see
   (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512 \
    | OPTION_MASK_ISA2_AVX10_2_UNSET)
 #define OPTION_MASK_ISA2_AVX10_2_UNSET \
-  (OPTION_MASK_ISA2_AVX10_2_256 | OPTION_MASK_ISA2_AVX10_2_512 \
-   | OPTION_MASK_ISA2_AMX_AVX512_UNSET)
+  (OPTION_MASK_ISA2_AVX10_2 | OPTION_MASK_ISA2_AMX_AVX512_UNSET)
 #define OPTION_MASK_ISA2_AMX_AVX512_UNSET OPTION_MASK_ISA2_AMX_AVX512
 #define OPTION_MASK_ISA2_AMX_TF32_UNSET OPTION_MASK_ISA2_AMX_TF32
 #define OPTION_MASK_ISA2_AMX_TRANSPOSE_UNSET OPTION_MASK_ISA2_AMX_TRANSPOSE
@@ -1398,21 +1394,11 @@ ix86_handle_option (struct gcc_options *opts,
        }
       return true;
 
-    case OPT_mavx10_2_256:
-      if (value)
-       {
-         opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_2_256_SET;
-         opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_256_SET;
-         opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
-         opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
-       }
-      return true;
-
     case OPT_mavx10_2:
       if (value)
        {
-         opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_2_512_SET;
-         opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_512_SET;
+         opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_2_SET;
+         opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_SET;
          opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
          opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
        }

diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h
index 996eff21dd7bf8324bf88aedaae91ec7f5312aa0..9a3d6448411d184b1904123786f1af772aafea18 100644 (file)
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -268,8 +268,7 @@ enum processor_features
   FEATURE_USER_MSR,
   FEATURE_AVX10_1_256,
   FEATURE_AVX10_1_512,
-  FEATURE_AVX10_2_256,
-  FEATURE_AVX10_2_512,
+  FEATURE_AVX10_2 = 116,
   FEATURE_AMX_AVX512,
   FEATURE_AMX_TF32,
   FEATURE_AMX_TRANSPOSE,

diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h
index 9dbbc6a19d8e9327d35ff51cf98ee705f93022d3..e6a1d36a77224b5319a3c9d9b4889b881aa237a5 100644 (file)
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -185,9 +185,7 @@ ISA_NAMES_TABLE_START
   ISA_NAMES_TABLE_ENTRY("usermsr", FEATURE_USER_MSR, P_NONE, "-musermsr")
   ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1_256, P_AVX10_1_256, "-mavx10.1-256")
   ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1_512, P_AVX10_1_512, "-mavx10.1-512")
-  ISA_NAMES_TABLE_ENTRY("avx10.2", FEATURE_AVX10_2_512, P_NONE, "-mavx10.2")
-  ISA_NAMES_TABLE_ENTRY("avx10.2-256", FEATURE_AVX10_2_256, P_NONE, "-mavx10.2-256")
-  ISA_NAMES_TABLE_ENTRY("avx10.2-512", FEATURE_AVX10_2_512, P_NONE, NULL)
+  ISA_NAMES_TABLE_ENTRY("avx10.2", FEATURE_AVX10_2, P_NONE, "-mavx10.2")
   ISA_NAMES_TABLE_ENTRY("amx-avx512", FEATURE_AMX_AVX512, P_NONE,
                        "-mamx-avx512")
   ISA_NAMES_TABLE_ENTRY("amx-tf32", FEATURE_AMX_TF32, P_NONE, "-mamx-tf32")

diff --git a/gcc/config/i386/avx10_2-512bf16intrin.h b/gcc/config/i386/avx10_2-512bf16intrin.h
index 307b14a878a70b161a8a9b22067835db9c421cff..21e4b369c9ebfd9c1ef893375715310d3ea3027e 100644 (file)
--- a/gcc/config/i386/avx10_2-512bf16intrin.h
+++ b/gcc/config/i386/avx10_2-512bf16intrin.h
@@ -28,11 +28,11 @@
 #ifndef _AVX10_2_512BF16INTRIN_H_INCLUDED
 #define _AVX10_2_512BF16INTRIN_H_INCLUDED
 
-#if !defined (__AVX10_2_512__)
+#if !defined (__AVX10_2__)
 #pragma GCC push_options
-#pragma GCC target("avx10.2-512")
-#define __DISABLE_AVX10_2_512__
-#endif /* __AVX10_2_512__ */
+#pragma GCC target("avx10.2")
+#define __DISABLE_AVX10_2__
+#endif /* __AVX10_2__ */
 
 extern __inline__ __m512bh
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
@@ -673,9 +673,9 @@ _mm512_cmp_pbh_mask (__m512bh __A, __m512bh __B, const int __imm)
 
 #endif /* __OPIMTIZE__ */
 
-#ifdef __DISABLE_AVX10_2_512__
-#undef __DISABLE_AVX10_2_512__
+#ifdef __DISABLE_AVX10_2__
+#undef __DISABLE_AVX10_2__
 #pragma GCC pop_options
-#endif /* __DISABLE_AVX10_2_512__ */
+#endif /* __DISABLE_AVX10_2__ */
 
 #endif /* _AVX10_2_512BF16INTRIN_H_INCLUDED */

diff --git a/gcc/config/i386/avx10_2-512convertintrin.h b/gcc/config/i386/avx10_2-512convertintrin.h
index a44481e0b4e9372369c9037bac0381254ebc3cb3..8007cf36d76a520cf040bd7d973aed3de893e6de 100644 (file)
--- a/gcc/config/i386/avx10_2-512convertintrin.h
+++ b/gcc/config/i386/avx10_2-512convertintrin.h
@@ -28,11 +28,11 @@
 #ifndef __AVX10_2_512CONVERTINTRIN_H_INCLUDED
 #define __AVX10_2_512CONVERTINTRIN_H_INCLUDED
 
-#ifndef __AVX10_2_512__
+#ifndef __AVX10_2__
 #pragma GCC push_options
-#pragma GCC target("avx10.2-512")
-#define __DISABLE_AVX10_2_512__
-#endif /* __AVX10_2_512__ */
+#pragma GCC target("avx10.2")
+#define __DISABLE_AVX10_2__
+#endif /* __AVX10_2__ */
 
 extern __inline __m512h
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
@@ -564,9 +564,9 @@ _mm512_maskz_cvtbf8_ph (__mmask32 __U, __m256i __A)
         (__m512i) _mm512_maskz_cvtepi8_epi16 (__U, __A), 8));
 }
 
-#ifdef __DISABLE_AVX10_2_512__
-#undef __DISABLE_AVX10_2_512__
+#ifdef __DISABLE_AVX10_2__
+#undef __DISABLE_AVX10_2__
 #pragma GCC pop_options
-#endif /* __DISABLE_AVX10_2_512__ */
+#endif /* __DISABLE_AVX10_2__ */
 
 #endif /* __AVX10_2_512CONVERTINTRIN_H_INCLUDED */

diff --git a/gcc/config/i386/avx10_2-512mediaintrin.h b/gcc/config/i386/avx10_2-512mediaintrin.h
index 5dedabc9e14f2f4bb70f4119c095a461e43251a6..43271e740dd8942e919f7cee45e406ac0b517dc5 100644 (file)
--- a/gcc/config/i386/avx10_2-512mediaintrin.h
+++ b/gcc/config/i386/avx10_2-512mediaintrin.h
@@ -28,11 +28,11 @@
 #ifndef _AVX10_2_512MEDIAINTRIN_H_INCLUDED
 #define _AVX10_2_512MEDIAINTRIN_H_INCLUDED
 
-#if !defined(__AVX10_2_512__)
+#if !defined(__AVX10_2__)
 #pragma GCC push_options
-#pragma GCC target("avx10.2-512")
-#define __DISABLE_AVX10_2_512__
-#endif /* __AVX10_2_512__ */
+#pragma GCC target("avx10.2")
+#define __DISABLE_AVX10_2__
+#endif /* __AVX10_2__ */
 
 extern __inline __m512i
 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
@@ -506,9 +506,9 @@ _mm512_maskz_mpsadbw_epu8 (__mmask32 __U, __m512i __X,
                                            (__mmask32)(U))
 #endif
 
-#ifdef __DISABLE_AVX10_2_512__
-#undef __DISABLE_AVX10_2_512__
+#ifdef __DISABLE_AVX10_2__
+#undef __DISABLE_AVX10_2__
 #pragma GCC pop_options
-#endif /* __DISABLE_AVX10_2_512__ */
+#endif /* __DISABLE_AVX10_2__ */
 
 #endif /* __AVX10_2_512MEDIAINTRIN_H_INCLUDED */

diff --git a/gcc/config/i386/avx10_2-512minmaxintrin.h b/gcc/config/i386/avx10_2-512minmaxintrin.h
index 3acdc568f27922b8cd56e5da6bf94972484269ca..a743346054bc4624600affb0e986c92412758c14 100644 (file)
--- a/gcc/config/i386/avx10_2-512minmaxintrin.h
+++ b/gcc/config/i386/avx10_2-512minmaxintrin.h
@@ -23,11 +23,11 @@
 #ifndef _AVX10_2_512MINMAXINTRIN_H_INCLUDED
 #define _AVX10_2_512MINMAXINTRIN_H_INCLUDED
 
-#if !defined (__AVX10_2_512__)
+#if !defined (__AVX10_2__)
 #pragma GCC push_options
-#pragma GCC target("avx10.2-512")
-#define __DISABLE_AVX10_2_512__
-#endif /* __AVX10_2_512__ */
+#pragma GCC target("avx10.2")
+#define __DISABLE_AVX10_2__
+#endif /* __AVX10_2__ */
 
 #ifdef __OPTIMIZE__
 extern __inline __m512bh
@@ -481,9 +481,9 @@ _mm512_maskz_minmax_round_ps (__mmask16 __U, __m512 __A, __m512 __B,
 
 #endif
 
-#ifdef __DISABLE_AVX10_2_512__
-#undef __DISABLE_AVX10_2_512__
+#ifdef __DISABLE_AVX10_2__
+#undef __DISABLE_AVX10_2__
 #pragma GCC pop_options
-#endif /* __DISABLE_AVX10_2_512__ */
+#endif /* __DISABLE_AVX10_2__ */
 
 #endif /* _AVX10_2_512MINMAXINTRIN_H_INCLUDED */

diff --git a/gcc/config/i386/avx10_2-512satcvtintrin.h b/gcc/config/i386/avx10_2-512satcvtintrin.h
index 255bacde7f023943c04b9bd28874c9fca74ec5b9..215b7fdadf374ad9d29889b295cacc9dab422872 100644 (file)
--- a/gcc/config/i386/avx10_2-512satcvtintrin.h
+++ b/gcc/config/i386/avx10_2-512satcvtintrin.h
@@ -28,11 +28,11 @@
 #ifndef _AVX10_2_512SATCVTINTRIN_H_INCLUDED
 #define _AVX10_2_512SATCVTINTRIN_H_INCLUDED
 
-#if !defined (__AVX10_2_512__)
+#if !defined (__AVX10_2__)
 #pragma GCC push_options
-#pragma GCC target("avx10.2-512")
-#define __DISABLE_AVX10_2_512__
-#endif /* __AVX10_2_512__ */
+#pragma GCC target("avx10.2")
+#define __DISABLE_AVX10_2__
+#endif /* __AVX10_2__ */
 
 extern __inline __m512i
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
@@ -1567,9 +1567,9 @@ _mm512_maskz_cvtts_roundps_epu64 (__mmask8 __U, __m256 __A, const int __R)
                                             (R)))
 #endif
 
-#ifdef __DISABLE_AVX10_2_512__
-#undef __DISABLE_AVX10_2_512__
+#ifdef __DISABLE_AVX10_2__
+#undef __DISABLE_AVX10_2__
 #pragma GCC pop_options
-#endif /* __DISABLE_AVX10_2_512__ */
+#endif /* __DISABLE_AVX10_2__ */
 
 #endif /* _AVX10_2_512SATCVTINTRIN_H_INCLUDED */

diff --git a/gcc/config/i386/avx10_2bf16intrin.h b/gcc/config/i386/avx10_2bf16intrin.h
index af3b4afe17f81457cc00aba14b8d0dc519dd1f3c..e6890fc2cfd6731005f03d84f49b8d3fe785cebc 100644 (file)
--- a/gcc/config/i386/avx10_2bf16intrin.h
+++ b/gcc/config/i386/avx10_2bf16intrin.h
@@ -28,11 +28,11 @@
 #ifndef _AVX10_2BF16INTRIN_H_INCLUDED
 #define _AVX10_2BF16INTRIN_H_INCLUDED
 
-#if !defined(__AVX10_2_256__)
+#if !defined(__AVX10_2__)
 #pragma GCC push_options
 #pragma GCC target("avx10.2")
-#define __DISABLE_AVX10_2_256__
-#endif /* __AVX10_2_256__ */
+#define __DISABLE_AVX10_2__
+#endif /* __AVX10_2__ */
 
 extern __inline__ __m256bh
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
@@ -1327,9 +1327,9 @@ _mm_comineq_sbh (__m128bh __A, __m128bh __B)
   return __builtin_ia32_vcomisbf16neq (__A, __B);
 }
 
-#ifdef __DISABLE_AVX10_2_256__
-#undef __DISABLE_AVX10_2_256__
+#ifdef __DISABLE_AVX10_2__
+#undef __DISABLE_AVX10_2__
 #pragma GCC pop_options
-#endif /* __DISABLE_AVX10_2_256__ */
+#endif /* __DISABLE_AVX10_2__ */
 
 #endif /* __AVX10_2BF16INTRIN_H_INCLUDED */

diff --git a/gcc/config/i386/avx10_2convertintrin.h b/gcc/config/i386/avx10_2convertintrin.h
index 4513b35050c05b7ab9ee6af9df5c35a4387d427f..6144723bb6bb1c8c0ec2c65c6b1f17dc6a041964 100644 (file)
--- a/gcc/config/i386/avx10_2convertintrin.h
+++ b/gcc/config/i386/avx10_2convertintrin.h
@@ -28,10 +28,10 @@
 #ifndef _AVX10_2CONVERTINTRIN_H_INCLUDED
 #define _AVX10_2CONVERTINTRIN_H_INCLUDED
 
-#if !defined(__AVX10_2_256__)
+#if !defined(__AVX10_2__)
 #pragma GCC push_options
 #pragma GCC target("avx10.2")
-#define __DISABLE_AVX10_2_256__
+#define __DISABLE_AVX10_2__
 #endif /* __AVX10_2__ */
 
 extern __inline __m128h
@@ -952,9 +952,9 @@ _mm256_maskz_cvtbf8_ph (__mmask16 __U, __m128i __A)
         (__m256i) _mm256_maskz_cvtepi8_epi16 (__U, __A), 8));
 }
 
-#ifdef __DISABLE_AVX10_2_256__
-#undef __DISABLE_AVX10_2_256__
+#ifdef __DISABLE_AVX10_2__
+#undef __DISABLE_AVX10_2__
 #pragma GCC pop_options
-#endif /* __DISABLE_AVX10_2_256__ */
+#endif /* __DISABLE_AVX10_2__ */
 
 #endif /* __AVX10_2CONVERTINTRIN_H_INCLUDED */

diff --git a/gcc/config/i386/avx10_2mediaintrin.h b/gcc/config/i386/avx10_2mediaintrin.h
index 19578a78ec5e1f475c44064bb61bf9d7d29f19e0..0993e8e4f5633db0d4bd65547d9d60ac9a16ebb0 100644 (file)
--- a/gcc/config/i386/avx10_2mediaintrin.h
+++ b/gcc/config/i386/avx10_2mediaintrin.h
@@ -28,11 +28,11 @@
 #ifndef _AVX10_2MEDIAINTRIN_H_INCLUDED
 #define _AVX10_2MEDIAINTRIN_H_INCLUDED
 
-#if !defined(__AVX10_2_256__)
+#if !defined(__AVX10_2__)
 #pragma GCC push_options
-#pragma GCC target("avx10.2-256")
-#define __DISABLE_AVX10_2_256__
-#endif /* __AVX10_2_256__ */
+#pragma GCC target("avx10.2")
+#define __DISABLE_AVX10_2__
+#endif /* __AVX10_2__ */
 
 #define _mm_dpbssd_epi32(W, A, B) \
   (__m128i) __builtin_ia32_vpdpbssd128 ((__v4si) (W), (__v4si) (A), (__v4si) (B))
@@ -831,9 +831,9 @@ _mm256_maskz_mpsadbw_epu8 (__mmask16 __U, __m256i __X,
 
 #endif
 
-#ifdef __DISABLE_AVX10_2_256__
-#undef __DISABLE_AVX10_2_256__
+#ifdef __DISABLE_AVX10_2__
+#undef __DISABLE_AVX10_2__
 #pragma GCC pop_options
-#endif /* __DISABLE_AVX10_2_256__ */
+#endif /* __DISABLE_AVX10_2__ */
 
 #endif /* __AVX10_2MEDIAINTRIN_H_INCLUDED */

diff --git a/gcc/config/i386/avx10_2minmaxintrin.h b/gcc/config/i386/avx10_2minmaxintrin.h
index 68d034b1ca2dbba48813f90661f7bf4f558fb5d0..0a4a253aa8caca3a2085461197d399d416e582b8 100644 (file)
--- a/gcc/config/i386/avx10_2minmaxintrin.h
+++ b/gcc/config/i386/avx10_2minmaxintrin.h
@@ -23,11 +23,11 @@
 #ifndef _AVX10_2MINMAXINTRIN_H_INCLUDED
 #define _AVX10_2MINMAXINTRIN_H_INCLUDED
 
-#if !defined(__AVX10_2_256__)
+#if !defined(__AVX10_2__)
 #pragma GCC push_options
 #pragma GCC target("avx10.2")
-#define __DISABLE_AVX10_2_256__
-#endif /* __AVX10_2_256__ */
+#define __DISABLE_AVX10_2__
+#endif /* __AVX10_2__ */
 
 #ifdef __OPTIMIZE__
 extern __inline __m128bh
@@ -876,9 +876,9 @@ _mm_maskz_minmax_round_ss (__mmask8 __U, __m128 __A, __m128 __B,
 
 #endif
 
-#ifdef __DISABLE_AVX10_2_256__
-#undef __DISABLE_AVX10_2_256__
+#ifdef __DISABLE_AVX10_2__
+#undef __DISABLE_AVX10_2__
 #pragma GCC pop_options
-#endif /* __DISABLE_AVX10_2_256__ */
+#endif /* __DISABLE_AVX10_2__ */
 
 #endif /* _AVX10_2MINMAXINTRIN_H_INCLUDED */

diff --git a/gcc/config/i386/avx10_2satcvtintrin.h b/gcc/config/i386/avx10_2satcvtintrin.h
index e68a066ae5e906adf7ce53e54d342a6cc0ba7cd3..78bcd729ff87a758c4f8d88841690c765c2e9b08 100644 (file)
--- a/gcc/config/i386/avx10_2satcvtintrin.h
+++ b/gcc/config/i386/avx10_2satcvtintrin.h
@@ -28,11 +28,11 @@
 #ifndef _AVX10_2SATCVTINTRIN_H_INCLUDED
 #define _AVX10_2SATCVTINTRIN_H_INCLUDED
 
-#if !defined (__AVX10_2_256__)
+#if !defined (__AVX10_2__)
 #pragma GCC push_options
 #pragma GCC target("avx10.2")
-#define __DISABLE_AVX10_2_256__
-#endif /* __AVX10_2_256__ */
+#define __DISABLE_AVX10_2__
+#endif /* __AVX10_2__ */
 
 extern __inline __m128i
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
@@ -1401,9 +1401,9 @@ _mm_cvtts_roundss_epu64 (__m128 __A, const int __R)
 #endif
 #endif /* __x86_64__ */
 
-#ifdef __DISABLE_AVX10_2_256__
-#undef __DISABLE_AVX10_2_256__
+#ifdef __DISABLE_AVX10_2__
+#undef __DISABLE_AVX10_2__
 #pragma GCC pop_options
-#endif /* __DISABLE_AVX10_2_256__ */
+#endif /* __DISABLE_AVX10_2__ */
 
 #endif /* _AVX10_2SATCVTINTRIN_H_INCLUDED */

diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index 1a31ceb2e7d8f1b4e78a31438419df5f68b54442..afd4ef06e9f7730fc575a3ca1624c5ae52f1227a 100644 (file)
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -171,11 +171,6 @@
 #define bit_AMX_AVX512  (1 << 7)
 #define bit_AMX_MOVRS  (1 << 8)
 
-/* AVX10 sub leaf (%eax == 0x24) */
-/* %ebx */
-#define bit_AVX10_256  (1 << 17)
-#define bit_AVX10_512  (1 << 18)
-
 /* Signatures for different CPU implementations as returned in uses
    of cpuid with level 0.  */
 #define signature_AMD_ebx      0x68747541

diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc
index ba13138dd1b22333cd5f695002d3e905c03951ca..82bdbafba4ea5e7eeefb793fb8ea854003c61fc5 100644 (file)
--- a/gcc/config/i386/driver-i386.cc
+++ b/gcc/config/i386/driver-i386.cc
@@ -627,7 +627,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
              if (has_feature (FEATURE_AVX512F))
                {
                  /* Assume Diamond Rapids.  */
-                 if (has_feature (FEATURE_AVX10_2_512))
+                 if (has_feature (FEATURE_AMX_TRANSPOSE))
                    cpu = "diamondrapids";
                  /* Assume Granite Rapids D.  */
                  else if (has_feature (FEATURE_AMX_COMPLEX))
@@ -910,12 +910,9 @@ const char *host_detect_local_cpu (int argc, const char **argv)
                                    isa_names_table[i].option, NULL);
              }
            /* Never push -mno-avx10.1-{256,512} under -march=native to
-              avoid unnecessary warnings when building libraries.
-              Never push -mno-avx10.x-256 under -march=native since
-              there are no such options.  */
+              avoid unnecessary warnings when building libraries.  */
            else if (isa_names_table[i].feature != FEATURE_AVX10_1_256
                     && isa_names_table[i].feature != FEATURE_AVX10_1_512
-                    && isa_names_table[i].feature != FEATURE_AVX10_2_256
                     && check_avx512_features (cpu_model, cpu_features2,
                                               isa_names_table[i].feature))
              options = concat (options, neg_option,

diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 712083b743534253abf0b86d3f2a5657cf693a6e..a142711408081f8f7ac719f811c0f54bdc22ded1 100644 (file)
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -510,18 +510,18 @@ BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS, CODE_FOR_movrsqi, "__built
 BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS, CODE_FOR_movrshi, "__builtin_ia32_movrshi", IX86_BUILTIN_MOVRSHI, UNKNOWN, (int) SHORT_FTYPE_PCSHORT)
 BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS, CODE_FOR_movrssi, "__builtin_ia32_movrssi", IX86_BUILTIN_MOVRSSI, UNKNOWN, (int) INT_FTYPE_PCINT)
 BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS, CODE_FOR_movrsdi, "__builtin_ia32_movrsdi", IX86_BUILTIN_MOVRSDI, UNKNOWN, (int) INT64_FTYPE_PCINT64)
-BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vmovrsbv64qi_mask, "__builtin_ia32_vmovrsb512_mask", IX86_BUILTIN_VMOVRSB_512, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_UDI)
-BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vmovrsdv16si_mask, "__builtin_ia32_vmovrsd512_mask", IX86_BUILTIN_VMOVRSD_512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_UHI)
-BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vmovrsqv8di_mask, "__builtin_ia32_vmovrsq512_mask", IX86_BUILTIN_VMOVRSQ_512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_UQI)
-BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vmovrswv32hi_mask, "__builtin_ia32_vmovrsw512_mask", IX86_BUILTIN_VMOVRSW_512, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_USI)
-BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vmovrsbv32qi_mask, "__builtin_ia32_vmovrsb256_mask", IX86_BUILTIN_VMOVRSB_256, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_USI)
-BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vmovrsdv8si_mask, "__builtin_ia32_vmovrsd256_mask", IX86_BUILTIN_VMOVRSD_256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_UQI)
-BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vmovrsqv4di_mask, "__builtin_ia32_vmovrsq256_mask", IX86_BUILTIN_VMOVRSQ_256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_UQI)
-BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vmovrswv16hi_mask, "__builtin_ia32_vmovrsw256_mask", IX86_BUILTIN_VMOVRSW_256, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_UHI)
-BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vmovrsbv16qi_mask, "__builtin_ia32_vmovrsb128_mask", IX86_BUILTIN_VMOVRSB_128, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_UHI)
-BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vmovrsdv4si_mask, "__builtin_ia32_vmovrsd128_mask", IX86_BUILTIN_VMOVRSD_128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_UQI)
-BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vmovrsqv2di_mask, "__builtin_ia32_vmovrsq128_mask", IX86_BUILTIN_VMOVRSQ_128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_UQI)
-BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vmovrswv8hi_mask, "__builtin_ia32_vmovrsw128_mask", IX86_BUILTIN_VMOVRSW_128, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_UQI)
+BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vmovrsbv64qi_mask, "__builtin_ia32_vmovrsb512_mask", IX86_BUILTIN_VMOVRSB_512, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_UDI)
+BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vmovrsdv16si_mask, "__builtin_ia32_vmovrsd512_mask", IX86_BUILTIN_VMOVRSD_512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_UHI)
+BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vmovrsqv8di_mask, "__builtin_ia32_vmovrsq512_mask", IX86_BUILTIN_VMOVRSQ_512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_UQI)
+BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vmovrswv32hi_mask, "__builtin_ia32_vmovrsw512_mask", IX86_BUILTIN_VMOVRSW_512, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_USI)
+BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vmovrsbv32qi_mask, "__builtin_ia32_vmovrsb256_mask", IX86_BUILTIN_VMOVRSB_256, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_USI)
+BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vmovrsdv8si_mask, "__builtin_ia32_vmovrsd256_mask", IX86_BUILTIN_VMOVRSD_256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_UQI)
+BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vmovrsqv4di_mask, "__builtin_ia32_vmovrsq256_mask", IX86_BUILTIN_VMOVRSQ_256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_UQI)
+BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vmovrswv16hi_mask, "__builtin_ia32_vmovrsw256_mask", IX86_BUILTIN_VMOVRSW_256, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_UHI)
+BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vmovrsbv16qi_mask, "__builtin_ia32_vmovrsb128_mask", IX86_BUILTIN_VMOVRSB_128, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_UHI)
+BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vmovrsdv4si_mask, "__builtin_ia32_vmovrsd128_mask", IX86_BUILTIN_VMOVRSD_128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_UQI)
+BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vmovrsqv2di_mask, "__builtin_ia32_vmovrsq128_mask", IX86_BUILTIN_VMOVRSQ_128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_UQI)
+BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_MOVRS | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vmovrswv8hi_mask, "__builtin_ia32_vmovrsw128_mask", IX86_BUILTIN_VMOVRSW_128, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_UQI)
 
 BDESC_END (SPECIAL_ARGS, PURE_ARGS)
 
@@ -1686,10 +1686,10 @@ BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3rnds2, "__builtin
 /* SM4 */
 BDESC (0, OPTION_MASK_ISA2_SM4, CODE_FOR_vsm4key4_v4si, "__builtin_ia32_vsm4key4128", IX86_BUILTIN_VSM4KEY4128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI)
 BDESC (0, OPTION_MASK_ISA2_SM4, CODE_FOR_vsm4key4_v8si, "__builtin_ia32_vsm4key4256", IX86_BUILTIN_VSM4KEY4256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_SM4 | OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vsm4key4_v16si, "__builtin_ia32_vsm4key4512", IX86_BUILTIN_VSM4KEY4512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_SM4 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vsm4key4_v16si, "__builtin_ia32_vsm4key4512", IX86_BUILTIN_VSM4KEY4512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI)
 BDESC (0, OPTION_MASK_ISA2_SM4, CODE_FOR_vsm4rnds4_v4si, "__builtin_ia32_vsm4rnds4128", IX86_BUILTIN_VSM4RNDS4128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI)
 BDESC (0, OPTION_MASK_ISA2_SM4, CODE_FOR_vsm4rnds4_v8si, "__builtin_ia32_vsm4rnds4256", IX86_BUILTIN_VSM4RNDS4256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_SM4 | OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vsm4rnds4_v16si, "__builtin_ia32_vsm4rnds4512", IX86_BUILTIN_VSM4RNDS4512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_SM4 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vsm4rnds4_v16si, "__builtin_ia32_vsm4rnds4512", IX86_BUILTIN_VSM4RNDS4512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI)
 
 /* SHA512 */
 BDESC (0, OPTION_MASK_ISA2_SHA512, CODE_FOR_vsha512msg1, "__builtin_ia32_vsha512msg1", IX86_BUILTIN_VSHA512MSG1, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI)
@@ -2768,32 +2768,32 @@ BDESC (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpdpws
 BDESC (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpdpwssds_v4si_maskz, "__builtin_ia32_vpdpwssds_v4si_maskz", IX86_BUILTIN_VPDPWSSDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
 
 /* AVXVNNIINT8 */
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbssd_v8si, "__builtin_ia32_vpdpbssd256", IX86_BUILTIN_VPDPBSSDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbssds_v8si, "__builtin_ia32_vpdpbssds256", IX86_BUILTIN_VPDPBSSDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbsud_v8si, "__builtin_ia32_vpdpbsud256", IX86_BUILTIN_VPDPBSUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbsuds_v8si, "__builtin_ia32_vpdpbsuds256", IX86_BUILTIN_VPDPBSUDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbuud_v8si, "__builtin_ia32_vpdpbuud256", IX86_BUILTIN_VPDPBUUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbuuds_v8si, "__builtin_ia32_vpdpbuuds256", IX86_BUILTIN_VPDPBUUDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbssd_v4si, "__builtin_ia32_vpdpbssd128", IX86_BUILTIN_VPDPBSSDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbssds_v4si, "__builtin_ia32_vpdpbssds128", IX86_BUILTIN_VPDPBSSDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbsud_v4si, "__builtin_ia32_vpdpbsud128", IX86_BUILTIN_VPDPBSUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbsuds_v4si, "__builtin_ia32_vpdpbsuds128", IX86_BUILTIN_VPDPBSUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbuud_v4si, "__builtin_ia32_vpdpbuud128", IX86_BUILTIN_VPDPBUUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbuuds_v4si, "__builtin_ia32_vpdpbuuds128", IX86_BUILTIN_VPDPBUUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssd_v8si, "__builtin_ia32_vpdpbssd256", IX86_BUILTIN_VPDPBSSDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssds_v8si, "__builtin_ia32_vpdpbssds256", IX86_BUILTIN_VPDPBSSDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsud_v8si, "__builtin_ia32_vpdpbsud256", IX86_BUILTIN_VPDPBSUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsuds_v8si, "__builtin_ia32_vpdpbsuds256", IX86_BUILTIN_VPDPBSUDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuud_v8si, "__builtin_ia32_vpdpbuud256", IX86_BUILTIN_VPDPBUUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuuds_v8si, "__builtin_ia32_vpdpbuuds256", IX86_BUILTIN_VPDPBUUDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssd_v4si, "__builtin_ia32_vpdpbssd128", IX86_BUILTIN_VPDPBSSDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssds_v4si, "__builtin_ia32_vpdpbssds128", IX86_BUILTIN_VPDPBSSDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsud_v4si, "__builtin_ia32_vpdpbsud128", IX86_BUILTIN_VPDPBSUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsuds_v4si, "__builtin_ia32_vpdpbsuds128", IX86_BUILTIN_VPDPBSUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuud_v4si, "__builtin_ia32_vpdpbuud128", IX86_BUILTIN_VPDPBUUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuuds_v4si, "__builtin_ia32_vpdpbuuds128", IX86_BUILTIN_VPDPBUUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
 
 /* AVXVNNIINT16 */
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwusd_v8si, "__builtin_ia32_vpdpwusd256", IX86_BUILTIN_VPDPWUSDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwusds_v8si, "__builtin_ia32_vpdpwusds256", IX86_BUILTIN_VPDPWUSDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwsud_v8si, "__builtin_ia32_vpdpwsud256", IX86_BUILTIN_VPDPWSUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwsuds_v8si, "__builtin_ia32_vpdpwsuds256", IX86_BUILTIN_VPDPWSUDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwuud_v8si, "__builtin_ia32_vpdpwuud256", IX86_BUILTIN_VPDPWUUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwuuds_v8si, "__builtin_ia32_vpdpwuuds256", IX86_BUILTIN_VPDPWUUDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwusd_v4si, "__builtin_ia32_vpdpwusd128", IX86_BUILTIN_VPDPWUSDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwusds_v4si, "__builtin_ia32_vpdpwusds128", IX86_BUILTIN_VPDPWUSDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwsud_v4si, "__builtin_ia32_vpdpwsud128", IX86_BUILTIN_VPDPWSUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwsuds_v4si, "__builtin_ia32_vpdpwsuds128", IX86_BUILTIN_VPDPWSUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwuud_v4si, "__builtin_ia32_vpdpwuud128", IX86_BUILTIN_VPDPWUUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
-BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwuuds_v4si, "__builtin_ia32_vpdpwuuds128", IX86_BUILTIN_VPDPWUUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusd_v8si, "__builtin_ia32_vpdpwusd256", IX86_BUILTIN_VPDPWUSDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusds_v8si, "__builtin_ia32_vpdpwusds256", IX86_BUILTIN_VPDPWUSDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsud_v8si, "__builtin_ia32_vpdpwsud256", IX86_BUILTIN_VPDPWSUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsuds_v8si, "__builtin_ia32_vpdpwsuds256", IX86_BUILTIN_VPDPWSUDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuud_v8si, "__builtin_ia32_vpdpwuud256", IX86_BUILTIN_VPDPWUUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuuds_v8si, "__builtin_ia32_vpdpwuuds256", IX86_BUILTIN_VPDPWUUDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusd_v4si, "__builtin_ia32_vpdpwusd128", IX86_BUILTIN_VPDPWUSDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusds_v4si, "__builtin_ia32_vpdpwusds128", IX86_BUILTIN_VPDPWUSDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsud_v4si, "__builtin_ia32_vpdpwsud128", IX86_BUILTIN_VPDPWSUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsuds_v4si, "__builtin_ia32_vpdpwsuds128", IX86_BUILTIN_VPDPWSUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuud_v4si, "__builtin_ia32_vpdpwuud128", IX86_BUILTIN_VPDPWUUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
+BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16 | OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuuds_v4si, "__builtin_ia32_vpdpwuuds128", IX86_BUILTIN_VPDPWUUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
 
 /* VPCLMULQDQ */
 BDESC (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpclmulqdq_v2di, "__builtin_ia32_vpclmulqdq_v2di", IX86_BUILTIN_VPCLMULQDQ2, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT)
@@ -3041,325 +3041,325 @@ BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_
 BDESC (OPTION_MASK_ISA_AVX512VL, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512vl_fmulc_v16hf_mask, "__builtin_ia32_vfmulcph256_mask", IX86_BUILTIN_VFMULCPH256_MASK, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UQI)
 
 /* AVX10.2.  */
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpbssd_v16si, "__builtin_ia32_vpdpbssd512", IX86_BUILTIN_VPDPBSSDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpbssds_v16si, "__builtin_ia32_vpdpbssds512", IX86_BUILTIN_VPDPBSSDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpbsud_v16si, "__builtin_ia32_vpdpbsud512", IX86_BUILTIN_VPDPBSUDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpbsuds_v16si, "__builtin_ia32_vpdpbsuds512", IX86_BUILTIN_VPDPBSUDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpbuud_v16si, "__builtin_ia32_vpdpbuud512", IX86_BUILTIN_VPDPBUUDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpbuuds_v16si, "__builtin_ia32_vpdpbuuds512", IX86_BUILTIN_VPDPBUUDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpbssd_v16si_mask, "__builtin_ia32_vpdpbssd_v16si_mask", IX86_BUILTIN_VPDPBSSDV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpbssd_v16si_maskz, "__builtin_ia32_vpdpbssd_v16si_maskz", IX86_BUILTIN_VPDPBSSDV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpbssds_v16si_mask, "__builtin_ia32_vpdpbssds_v16si_mask", IX86_BUILTIN_VPDPBSSDSV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpbssds_v16si_maskz, "__builtin_ia32_vpdpbssds_v16si_maskz", IX86_BUILTIN_VPDPBSSDSV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpbsud_v16si_mask, "__builtin_ia32_vpdpbsud_v16si_mask", IX86_BUILTIN_VPDPBSUDV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpbsud_v16si_maskz, "__builtin_ia32_vpdpbsud_v16si_maskz", IX86_BUILTIN_VPDPBSUDV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpbsuds_v16si_mask, "__builtin_ia32_vpdpbsuds_v16si_mask", IX86_BUILTIN_VPDPBSUDSV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpbsuds_v16si_maskz, "__builtin_ia32_vpdpbsuds_v16si_maskz", IX86_BUILTIN_VPDPBSUDSV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpbuud_v16si_mask, "__builtin_ia32_vpdpbuud_v16si_mask", IX86_BUILTIN_VPDPBUUDV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpbuud_v16si_maskz, "__builtin_ia32_vpdpbuud_v16si_maskz", IX86_BUILTIN_VPDPBUUDV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpbuuds_v16si_mask, "__builtin_ia32_vpdpbuuds_v16si_mask", IX86_BUILTIN_VPDPBUUDSV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpbuuds_v16si_maskz, "__builtin_ia32_vpdpbuuds_v16si_maskz", IX86_BUILTIN_VPDPBUUDSV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbssd_v8si_mask, "__builtin_ia32_vpdpbssd_v8si_mask", IX86_BUILTIN_VPDPBSSDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbssd_v8si_maskz, "__builtin_ia32_vpdpbssd_v8si_maskz", IX86_BUILTIN_VPDPBSSDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbssds_v8si_mask, "__builtin_ia32_vpdpbssds_v8si_mask", IX86_BUILTIN_VPDPBSSDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbssds_v8si_maskz, "__builtin_ia32_vpdpbssds_v8si_maskz", IX86_BUILTIN_VPDPBSSDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbsud_v8si_mask, "__builtin_ia32_vpdpbsud_v8si_mask", IX86_BUILTIN_VPDPBSUDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbsud_v8si_maskz, "__builtin_ia32_vpdpbsud_v8si_maskz", IX86_BUILTIN_VPDPBSUDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbsuds_v8si_mask, "__builtin_ia32_vpdpbsuds_v8si_mask", IX86_BUILTIN_VPDPBSUDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbsuds_v8si_maskz, "__builtin_ia32_vpdpbsuds_v8si_maskz", IX86_BUILTIN_VPDPBSUDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbuud_v8si_mask, "__builtin_ia32_vpdpbuud_v8si_mask", IX86_BUILTIN_VPDPBUUDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbuud_v8si_maskz, "__builtin_ia32_vpdpbuud_v8si_maskz", IX86_BUILTIN_VPDPBUUDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbuuds_v8si_mask, "__builtin_ia32_vpdpbuuds_v8si_mask", IX86_BUILTIN_VPDPBUUDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbuuds_v8si_maskz, "__builtin_ia32_vpdpbuuds_v8si_maskz", IX86_BUILTIN_VPDPBUUDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbssd_v4si_mask, "__builtin_ia32_vpdpbssd_v4si_mask", IX86_BUILTIN_VPDPBSSDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbssd_v4si_maskz, "__builtin_ia32_vpdpbssd_v4si_maskz", IX86_BUILTIN_VPDPBSSDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbssds_v4si_mask, "__builtin_ia32_vpdpbssds_v4si_mask", IX86_BUILTIN_VPDPBSSDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbssds_v4si_maskz, "__builtin_ia32_vpdpbssds_v4si_maskz", IX86_BUILTIN_VPDPBSSDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbsud_v4si_mask, "__builtin_ia32_vpdpbsud_v4si_mask", IX86_BUILTIN_VPDPBSUDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbsud_v4si_maskz, "__builtin_ia32_vpdpbsud_v4si_maskz", IX86_BUILTIN_VPDPBSUDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbsuds_v4si_mask, "__builtin_ia32_vpdpbsuds_v4si_mask", IX86_BUILTIN_VPDPBSUDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbsuds_v4si_maskz, "__builtin_ia32_vpdpbsuds_v4si_maskz", IX86_BUILTIN_VPDPBSUDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbuud_v4si_mask, "__builtin_ia32_vpdpbuud_v4si_mask", IX86_BUILTIN_VPDPBUUDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbuud_v4si_maskz, "__builtin_ia32_vpdpbuud_v4si_maskz", IX86_BUILTIN_VPDPBUUDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbuuds_v4si_mask, "__builtin_ia32_vpdpbuuds_v4si_mask", IX86_BUILTIN_VPDPBUUDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpbuuds_v4si_maskz, "__builtin_ia32_vpdpbuuds_v4si_maskz", IX86_BUILTIN_VPDPBUUDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpwsud_v16si, "__builtin_ia32_vpdpwsud512", IX86_BUILTIN_VPDPWSUDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpwsuds_v16si, "__builtin_ia32_vpdpwsuds512", IX86_BUILTIN_VPDPWSUDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpwusd_v16si, "__builtin_ia32_vpdpwusd512", IX86_BUILTIN_VPDPWUSDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpwusds_v16si, "__builtin_ia32_vpdpwusds512", IX86_BUILTIN_VPDPWUSDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpwuud_v16si, "__builtin_ia32_vpdpwuud512", IX86_BUILTIN_VPDPWUUDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpwuuds_v16si, "__builtin_ia32_vpdpwuuds512", IX86_BUILTIN_VPDPWUUDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpwsud_v16si_mask, "__builtin_ia32_vpdpwsud_v16si_mask", IX86_BUILTIN_VPDPWSUDV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpwsud_v16si_maskz, "__builtin_ia32_vpdpwsud_v16si_maskz", IX86_BUILTIN_VPDPWSUDV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpwsuds_v16si_mask, "__builtin_ia32_vpdpwsuds_v16si_mask", IX86_BUILTIN_VPDPWSUDSV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpwsuds_v16si_maskz, "__builtin_ia32_vpdpwsuds_v16si_maskz", IX86_BUILTIN_VPDPWSUDSV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpwusd_v16si_mask, "__builtin_ia32_vpdpwusd_v16si_mask", IX86_BUILTIN_VPDPWUSDV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpwusd_v16si_maskz, "__builtin_ia32_vpdpwusd_v16si_maskz", IX86_BUILTIN_VPDPWUSDV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpwusds_v16si_mask, "__builtin_ia32_vpdpwusds_v16si_mask", IX86_BUILTIN_VPDPWUSDSV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpwusds_v16si_maskz, "__builtin_ia32_vpdpwusds_v16si_maskz", IX86_BUILTIN_VPDPWUSDSV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpwuud_v16si_mask, "__builtin_ia32_vpdpwuud_v16si_mask", IX86_BUILTIN_VPDPWUUDV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpwuud_v16si_maskz, "__builtin_ia32_vpdpwuud_v16si_maskz", IX86_BUILTIN_VPDPWUUDV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpwuuds_v16si_mask, "__builtin_ia32_vpdpwuuds_v16si_mask", IX86_BUILTIN_VPDPWUUDSV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vpdpwuuds_v16si_maskz, "__builtin_ia32_vpdpwuuds_v16si_maskz", IX86_BUILTIN_VPDPWUUDSV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwsud_v8si_mask, "__builtin_ia32_vpdpwsud_v8si_mask", IX86_BUILTIN_VPDPWSUDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwsud_v8si_maskz, "__builtin_ia32_vpdpwsud_v8si_maskz", IX86_BUILTIN_VPDPWSUDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwsuds_v8si_mask, "__builtin_ia32_vpdpwsuds_v8si_mask", IX86_BUILTIN_VPDPWSUDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwsuds_v8si_maskz, "__builtin_ia32_vpdpwsuds_v8si_maskz", IX86_BUILTIN_VPDPWSUDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwusd_v8si_mask, "__builtin_ia32_vpdpwusd_v8si_mask", IX86_BUILTIN_VPDPWUSDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwusd_v8si_maskz, "__builtin_ia32_vpdpwusd_v8si_maskz", IX86_BUILTIN_VPDPWUSDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwusds_v8si_mask, "__builtin_ia32_vpdpwusds_v8si_mask", IX86_BUILTIN_VPDPWUSDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwusds_v8si_maskz, "__builtin_ia32_vpdpwusds_v8si_maskz", IX86_BUILTIN_VPDPWUSDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwuud_v8si_mask, "__builtin_ia32_vpdpwuud_v8si_mask", IX86_BUILTIN_VPDPWUUDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwuud_v8si_maskz, "__builtin_ia32_vpdpwuud_v8si_maskz", IX86_BUILTIN_VPDPWUUDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwuuds_v8si_mask, "__builtin_ia32_vpdpwuuds_v8si_mask", IX86_BUILTIN_VPDPWUUDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwuuds_v8si_maskz, "__builtin_ia32_vpdpwuuds_v8si_maskz", IX86_BUILTIN_VPDPWUUDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwsud_v4si_mask, "__builtin_ia32_vpdpwsud_v4si_mask", IX86_BUILTIN_VPDPWSUDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwsud_v4si_maskz, "__builtin_ia32_vpdpwsud_v4si_maskz", IX86_BUILTIN_VPDPWSUDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwsuds_v4si_mask, "__builtin_ia32_vpdpwsuds_v4si_mask", IX86_BUILTIN_VPDPWSUDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwsuds_v4si_maskz, "__builtin_ia32_vpdpwsuds_v4si_maskz", IX86_BUILTIN_VPDPWSUDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwusd_v4si_mask, "__builtin_ia32_vpdpwusd_v4si_mask", IX86_BUILTIN_VPDPWUSDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwusd_v4si_maskz, "__builtin_ia32_vpdpwusd_v4si_maskz", IX86_BUILTIN_VPDPWUSDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwusds_v4si_mask, "__builtin_ia32_vpdpwusds_v4si_mask", IX86_BUILTIN_VPDPWUSDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwusds_v4si_maskz, "__builtin_ia32_vpdpwusds_v4si_maskz", IX86_BUILTIN_VPDPWUSDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwuud_v4si_mask, "__builtin_ia32_vpdpwuud_v4si_mask", IX86_BUILTIN_VPDPWUUDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwuud_v4si_maskz, "__builtin_ia32_vpdpwuud_v4si_maskz", IX86_BUILTIN_VPDPWUUDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwuuds_v4si_mask, "__builtin_ia32_vpdpwuuds_v4si_mask", IX86_BUILTIN_VPDPWUUDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vpdpwuuds_v4si_maskz, "__builtin_ia32_vpdpwuuds_v4si_maskz", IX86_BUILTIN_VPDPWUUDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vdpphps_v16sf_mask, "__builtin_ia32_vdpphps512_mask", IX86_BUILTIN_VDPPHPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vdpphps_v16sf_maskz, "__builtin_ia32_vdpphps512_maskz", IX86_BUILTIN_VDPPHPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vdpphps_v8sf_mask, "__builtin_ia32_vdpphps256_mask", IX86_BUILTIN_VDPPHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vdpphps_v8sf_maskz, "__builtin_ia32_vdpphps256_maskz", IX86_BUILTIN_VDPPHPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vdpphps_v4sf_mask, "__builtin_ia32_vdpphps128_mask", IX86_BUILTIN_VDPPHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vdpphps_v4sf_maskz, "__builtin_ia32_vdpphps128_maskz", IX86_BUILTIN_VDPPHPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_mpsadbw, "__builtin_ia32_mpsadbw512", IX86_BUILTIN_AVX10_2_MPSADBW, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_mpsadbw_mask, "__builtin_ia32_mpsadbw512_mask", IX86_BUILTIN_VMPSADBW_V32HI_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx2_mpsadbw_mask, "__builtin_ia32_mpsadbw256_mask", IX86_BUILTIN_VMPSADBW_V16HI_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_sse4_1_mpsadbw_mask, "__builtin_ia32_mpsadbw128_mask", IX86_BUILTIN_VMPSADBW_V8HI_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvt2ps2phx_v16hf_mask, "__builtin_ia32_vcvt2ps2phx256_mask", IX86_BUILTIN_VCVT2PS2PHX_V16HF_MASK, UNKNOWN, (int) V16HF_FTYPE_V8SF_V8SF_V16HF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvt2ps2phx_v8hf_mask, "__builtin_ia32_vcvt2ps2phx128_mask", IX86_BUILTIN_VCVT2PS2PHX_V8HF_MASK, UNKNOWN, (int) V8HF_FTYPE_V4SF_V4SF_V8HF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtbiasph2bf8v8hf, "__builtin_ia32_vcvtbiasph2bf8128", IX86_BUILTIN_VCVTBIASPH2BF8128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtbiasph2bf8v8hf_mask, "__builtin_ia32_vcvtbiasph2bf8128_mask", IX86_BUILTIN_VCVTBIASPH2BF8128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtbiasph2bf8v16hf_mask, "__builtin_ia32_vcvtbiasph2bf8256_mask", IX86_BUILTIN_VCVTBIASPH2BF8256_MASK, UNKNOWN, (int) V16QI_FTYPE_V32QI_V16HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vcvtbiasph2bf8v32hf_mask, "__builtin_ia32_vcvtbiasph2bf8512_mask", IX86_BUILTIN_VCVTBIASPH2BF8512_MASK, UNKNOWN, (int) V32QI_FTYPE_V64QI_V32HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtbiasph2bf8sv8hf, "__builtin_ia32_vcvtbiasph2bf8s128", IX86_BUILTIN_VCVTBIASPH2BF8S128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtbiasph2bf8sv8hf_mask, "__builtin_ia32_vcvtbiasph2bf8s128_mask", IX86_BUILTIN_VCVTBIASPH2BF8S128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtbiasph2bf8sv16hf_mask, "__builtin_ia32_vcvtbiasph2bf8s256_mask", IX86_BUILTIN_VCVTBIASPH2BF8S256_MASK, UNKNOWN, (int) V16QI_FTYPE_V32QI_V16HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vcvtbiasph2bf8sv32hf_mask, "__builtin_ia32_vcvtbiasph2bf8s512_mask", IX86_BUILTIN_VCVTBIASPH2BF8S512_MASK, UNKNOWN, (int) V32QI_FTYPE_V64QI_V32HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtbiasph2hf8v8hf, "__builtin_ia32_vcvtbiasph2hf8128", IX86_BUILTIN_VCVTBIASPH2HF8128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtbiasph2hf8v8hf_mask, "__builtin_ia32_vcvtbiasph2hf8128_mask", IX86_BUILTIN_VCVTBIASPH2HF8128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtbiasph2hf8v16hf_mask, "__builtin_ia32_vcvtbiasph2hf8256_mask", IX86_BUILTIN_VCVTBIASPH2HF8256_MASK, UNKNOWN, (int) V16QI_FTYPE_V32QI_V16HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vcvtbiasph2hf8v32hf_mask, "__builtin_ia32_vcvtbiasph2hf8512_mask", IX86_BUILTIN_VCVTBIASPH2HF8512_MASK, UNKNOWN, (int) V32QI_FTYPE_V64QI_V32HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtbiasph2hf8sv8hf, "__builtin_ia32_vcvtbiasph2hf8s128", IX86_BUILTIN_VCVTBIASPH2HF8S128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtbiasph2hf8sv8hf_mask, "__builtin_ia32_vcvtbiasph2hf8s128_mask", IX86_BUILTIN_VCVTBIASPH2HF8S128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtbiasph2hf8sv16hf_mask, "__builtin_ia32_vcvtbiasph2hf8s256_mask", IX86_BUILTIN_VCVTBIASPH2HF8S256_MASK, UNKNOWN, (int) V16QI_FTYPE_V32QI_V16HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vcvtbiasph2hf8sv32hf_mask, "__builtin_ia32_vcvtbiasph2hf8s512_mask", IX86_BUILTIN_VCVTBIASPH2HF8S512_MASK, UNKNOWN, (int) V32QI_FTYPE_V64QI_V32HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvt2ph2bf8v8hf_mask, "__builtin_ia32_vcvt2ph2bf8128_mask", IX86_BUILTIN_VCVT2PH2BF8128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V8HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvt2ph2bf8v16hf_mask, "__builtin_ia32_vcvt2ph2bf8256_mask", IX86_BUILTIN_VCVT2PH2BF8256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HF_V16HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vcvt2ph2bf8v32hf_mask, "__builtin_ia32_vcvt2ph2bf8512_mask", IX86_BUILTIN_VCVT2PH2BF8512_MASK, UNKNOWN, (int) V64QI_FTYPE_V32HF_V32HF_V64QI_UDI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvt2ph2bf8sv8hf_mask, "__builtin_ia32_vcvt2ph2bf8s128_mask", IX86_BUILTIN_VCVT2PH2BF8S128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V8HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvt2ph2bf8sv16hf_mask, "__builtin_ia32_vcvt2ph2bf8s256_mask", IX86_BUILTIN_VCVT2PH2BF8S256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HF_V16HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vcvt2ph2bf8sv32hf_mask, "__builtin_ia32_vcvt2ph2bf8s512_mask", IX86_BUILTIN_VCVT2PH2BF8S512_MASK, UNKNOWN, (int) V64QI_FTYPE_V32HF_V32HF_V64QI_UDI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvt2ph2hf8v8hf_mask, "__builtin_ia32_vcvt2ph2hf8128_mask", IX86_BUILTIN_VCVT2PH2HF8128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V8HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvt2ph2hf8v16hf_mask, "__builtin_ia32_vcvt2ph2hf8256_mask", IX86_BUILTIN_VCVT2PH2HF8256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HF_V16HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vcvt2ph2hf8v32hf_mask, "__builtin_ia32_vcvt2ph2hf8512_mask", IX86_BUILTIN_VCVT2PH2HF8512_MASK, UNKNOWN, (int) V64QI_FTYPE_V32HF_V32HF_V64QI_UDI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvt2ph2hf8sv8hf_mask, "__builtin_ia32_vcvt2ph2hf8s128_mask", IX86_BUILTIN_VCVT2PH2HF8S128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V8HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvt2ph2hf8sv16hf_mask, "__builtin_ia32_vcvt2ph2hf8s256_mask", IX86_BUILTIN_VCVT2PH2HF8S256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HF_V16HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vcvt2ph2hf8sv32hf_mask, "__builtin_ia32_vcvt2ph2hf8s512_mask", IX86_BUILTIN_VCVT2PH2HF8S512_MASK, UNKNOWN, (int) V64QI_FTYPE_V32HF_V32HF_V64QI_UDI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtph2bf8v8hf_mask, "__builtin_ia32_vcvtph2bf8128_mask", IX86_BUILTIN_VCVTPH2BF8128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V16QI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtph2bf8v16hf_mask, "__builtin_ia32_vcvtph2bf8256_mask", IX86_BUILTIN_VCVTPH2BF8256_MASK, UNKNOWN, (int) V16QI_FTYPE_V16HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vcvtph2bf8v32hf_mask, "__builtin_ia32_vcvtph2bf8512_mask", IX86_BUILTIN_VCVTPH2BF8512_MASK, UNKNOWN, (int) V32QI_FTYPE_V32HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtph2bf8sv8hf_mask, "__builtin_ia32_vcvtph2bf8s128_mask", IX86_BUILTIN_VCVTPH2BF8S128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V16QI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtph2bf8sv16hf_mask, "__builtin_ia32_vcvtph2bf8s256_mask", IX86_BUILTIN_VCVTPH2BF8S256_MASK, UNKNOWN, (int) V16QI_FTYPE_V16HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vcvtph2bf8sv32hf_mask, "__builtin_ia32_vcvtph2bf8s512_mask", IX86_BUILTIN_VCVTPH2BF8S512_MASK, UNKNOWN, (int) V32QI_FTYPE_V32HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtph2hf8v8hf_mask, "__builtin_ia32_vcvtph2hf8128_mask", IX86_BUILTIN_VCVTPH2HF8128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V16QI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtph2hf8v16hf_mask, "__builtin_ia32_vcvtph2hf8256_mask", IX86_BUILTIN_VCVTPH2HF8256_MASK, UNKNOWN, (int) V16QI_FTYPE_V16HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vcvtph2hf8v32hf_mask, "__builtin_ia32_vcvtph2hf8512_mask", IX86_BUILTIN_VCVTPH2HF8512_MASK, UNKNOWN, (int) V32QI_FTYPE_V32HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtph2hf8sv8hf_mask, "__builtin_ia32_vcvtph2hf8s128_mask", IX86_BUILTIN_VCVTPH2HF8S128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V16QI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvtph2hf8sv16hf_mask, "__builtin_ia32_vcvtph2hf8s256_mask", IX86_BUILTIN_VCVTPH2HF8S256_MASK, UNKNOWN, (int) V16QI_FTYPE_V16HF_V16QI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vcvtph2hf8sv32hf_mask, "__builtin_ia32_vcvtph2hf8s512_mask", IX86_BUILTIN_VCVTPH2HF8S512_MASK, UNKNOWN, (int) V32QI_FTYPE_V32HF_V32QI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvthf82phv8hf_mask, "__builtin_ia32_vcvthf82ph128_mask", IX86_BUILTIN_VCVTHF82PH128_MASK, UNKNOWN, (int) V8HF_FTYPE_V16QI_V8HF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_vcvthf82phv16hf_mask, "__builtin_ia32_vcvthf82ph256_mask", IX86_BUILTIN_VCVTHF82PH256_MASK, UNKNOWN, (int) V16HF_FTYPE_V16QI_V16HF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_vcvthf82phv32hf_mask, "__builtin_ia32_vcvthf82ph512_mask", IX86_BUILTIN_VCVTHF82PH512_MASK, UNKNOWN, (int) V32HF_FTYPE_V32QI_V32HF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_addbf16_v32bf, "__builtin_ia32_addbf16512", IX86_BUILTIN_ADDBF16512, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_addbf16_v32bf_mask, "__builtin_ia32_addbf16512_mask", IX86_BUILTIN_ADDBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_addbf16_v16bf, "__builtin_ia32_addbf16256", IX86_BUILTIN_ADDBF16256, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_addbf16_v16bf_mask, "__builtin_ia32_addbf16256_mask", IX86_BUILTIN_ADDBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_addbf16_v8bf, "__builtin_ia32_addbf16128", IX86_BUILTIN_ADDBF16128, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_addbf16_v8bf_mask, "__builtin_ia32_addbf16128_mask", IX86_BUILTIN_ADDBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_subbf16_v32bf, "__builtin_ia32_subbf16512", IX86_BUILTIN_SUBBF16512, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_subbf16_v32bf_mask, "__builtin_ia32_subbf16512_mask", IX86_BUILTIN_SUBBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_subbf16_v16bf, "__builtin_ia32_subbf16256", IX86_BUILTIN_SUBBF16256, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_subbf16_v16bf_mask, "__builtin_ia32_subbf16256_mask", IX86_BUILTIN_SUBBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_subbf16_v8bf, "__builtin_ia32_subbf16128", IX86_BUILTIN_SUBBF16128, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_subbf16_v8bf_mask, "__builtin_ia32_subbf16128_mask", IX86_BUILTIN_SUBBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_mulbf16_v32bf, "__builtin_ia32_mulbf16512", IX86_BUILTIN_MULBF16512, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_mulbf16_v32bf_mask, "__builtin_ia32_mulbf16512_mask", IX86_BUILTIN_MULBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_mulbf16_v16bf, "__builtin_ia32_mulbf16256", IX86_BUILTIN_MULBF16256, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_mulbf16_v16bf_mask, "__builtin_ia32_mulbf16256_mask", IX86_BUILTIN_MULBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_mulbf16_v8bf, "__builtin_ia32_mulbf16128", IX86_BUILTIN_MULBF16128, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_mulbf16_v8bf_mask, "__builtin_ia32_mulbf16128_mask", IX86_BUILTIN_MULBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_divbf16_v32bf, "__builtin_ia32_divbf16512", IX86_BUILTIN_DIVBF16512, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_divbf16_v32bf_mask, "__builtin_ia32_divbf16512_mask", IX86_BUILTIN_DIVBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_divbf16_v16bf, "__builtin_ia32_divbf16256", IX86_BUILTIN_DIVBF16256, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_divbf16_v16bf_mask, "__builtin_ia32_divbf16256_mask", IX86_BUILTIN_DIVBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_divbf16_v8bf, "__builtin_ia32_divbf16128", IX86_BUILTIN_DIVBF16128, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_divbf16_v8bf_mask, "__builtin_ia32_divbf16128_mask", IX86_BUILTIN_DIVBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_smaxbf16_v32bf, "__builtin_ia32_maxbf16512", IX86_BUILTIN_MAXBF16512, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_smaxbf16_v32bf_mask, "__builtin_ia32_maxbf16512_mask", IX86_BUILTIN_MAXBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_smaxbf16_v16bf, "__builtin_ia32_maxbf16256", IX86_BUILTIN_MAXBF16256, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_smaxbf16_v16bf_mask, "__builtin_ia32_maxbf16256_mask", IX86_BUILTIN_MAXBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_smaxbf16_v8bf, "__builtin_ia32_maxbf16128", IX86_BUILTIN_MAXBF16128, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_smaxbf16_v8bf_mask, "__builtin_ia32_maxbf16128_mask", IX86_BUILTIN_MAXBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_sminbf16_v32bf, "__builtin_ia32_minbf16512", IX86_BUILTIN_MINBF16512, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_sminbf16_v32bf_mask, "__builtin_ia32_minbf16512_mask", IX86_BUILTIN_MINBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_sminbf16_v16bf, "__builtin_ia32_minbf16256", IX86_BUILTIN_MINBF16256, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_sminbf16_v16bf_mask, "__builtin_ia32_minbf16256_mask", IX86_BUILTIN_MINBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_sminbf16_v8bf, "__builtin_ia32_minbf16128", IX86_BUILTIN_MINBF16128, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_sminbf16_v8bf_mask, "__builtin_ia32_minbf16128_mask", IX86_BUILTIN_MINBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_scalefbf16_v32bf, "__builtin_ia32_scalefbf16512", IX86_BUILTIN_SCALEFBF16512, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_scalefbf16_v32bf_mask, "__builtin_ia32_scalefbf16512_mask", IX86_BUILTIN_SCALEFBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_scalefbf16_v16bf, "__builtin_ia32_scalefbf16256", IX86_BUILTIN_SCALEFBF16256, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_scalefbf16_v16bf_mask, "__builtin_ia32_scalefbf16256_mask", IX86_BUILTIN_SCALEFBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_scalefbf16_v8bf, "__builtin_ia32_scalefbf16128", IX86_BUILTIN_SCALEFBF16128, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_scalefbf16_v8bf_mask, "__builtin_ia32_scalefbf16128_mask", IX86_BUILTIN_SCALEFBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_fmaddbf16_v32bf_mask, "__builtin_ia32_fmaddbf16512_mask", IX86_BUILTIN_FMADDBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_fmaddbf16_v32bf_mask3, "__builtin_ia32_fmaddbf16512_mask3", IX86_BUILTIN_FMADDBF16512_MASK3, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_fmaddbf16_v32bf_maskz, "__builtin_ia32_fmaddbf16512_maskz", IX86_BUILTIN_FMADDBF16512_MASKZ, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fmaddbf16_v16bf_mask, "__builtin_ia32_fmaddbf16256_mask", IX86_BUILTIN_FMADDBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fmaddbf16_v16bf_mask3, "__builtin_ia32_fmaddbf16256_mask3", IX86_BUILTIN_FMADDBF16256_MASK3, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fmaddbf16_v16bf_maskz, "__builtin_ia32_fmaddbf16256_maskz", IX86_BUILTIN_FMADDBF16256_MASKZ, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fmaddbf16_v8bf_mask, "__builtin_ia32_fmaddbf16128_mask", IX86_BUILTIN_FMADDBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fmaddbf16_v8bf_mask3, "__builtin_ia32_fmaddbf16128_mask3", IX86_BUILTIN_FMADDBF16128_MASK3, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fmaddbf16_v8bf_maskz, "__builtin_ia32_fmaddbf16128_maskz", IX86_BUILTIN_FMADDBF16128_MASKZ, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_fmsubbf16_v32bf_mask, "__builtin_ia32_fmsubbf16512_mask", IX86_BUILTIN_FMSUBBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_fmsubbf16_v32bf_mask3, "__builtin_ia32_fmsubbf16512_mask3", IX86_BUILTIN_FMSUBBF16512_MASK3, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_fmsubbf16_v32bf_maskz, "__builtin_ia32_fmsubbf16512_maskz", IX86_BUILTIN_FMSUBBF16512_MASKZ, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fmsubbf16_v16bf_mask, "__builtin_ia32_fmsubbf16256_mask", IX86_BUILTIN_FMSUBBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fmsubbf16_v16bf_mask3, "__builtin_ia32_fmsubbf16256_mask3", IX86_BUILTIN_FMSUBBF16256_MASK3, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fmsubbf16_v16bf_maskz, "__builtin_ia32_fmsubbf16256_maskz", IX86_BUILTIN_FMSUBBF16256_MASKZ, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fmsubbf16_v8bf_mask, "__builtin_ia32_fmsubbf16128_mask", IX86_BUILTIN_FMSUBBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fmsubbf16_v8bf_mask3, "__builtin_ia32_fmsubbf16128_mask3", IX86_BUILTIN_FMSUBBF16128_MASK3, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fmsubbf16_v8bf_maskz, "__builtin_ia32_fmsubbf16128_maskz", IX86_BUILTIN_FMSUBBF16128_MASKZ, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_fnmaddbf16_v32bf_mask, "__builtin_ia32_fnmaddbf16512_mask", IX86_BUILTIN_FNMADDBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_fnmaddbf16_v32bf_mask3, "__builtin_ia32_fnmaddbf16512_mask3", IX86_BUILTIN_FNMADDBF16512_MASK3, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_fnmaddbf16_v32bf_maskz, "__builtin_ia32_fnmaddbf16512_maskz", IX86_BUILTIN_FNMADDBF16512_MASKZ, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fnmaddbf16_v16bf_mask, "__builtin_ia32_fnmaddbf16256_mask", IX86_BUILTIN_FNMADDBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fnmaddbf16_v16bf_mask3, "__builtin_ia32_fnmaddbf16256_mask3", IX86_BUILTIN_FNMADDBF16256_MASK3, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fnmaddbf16_v16bf_maskz, "__builtin_ia32_fnmaddbf16256_maskz", IX86_BUILTIN_FNMADDBF16256_MASKZ, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fnmaddbf16_v8bf_mask, "__builtin_ia32_fnmaddbf16128_mask", IX86_BUILTIN_FNMADDBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fnmaddbf16_v8bf_mask3, "__builtin_ia32_fnmaddbf16128_mask3", IX86_BUILTIN_FNMADDBF16128_MASK3, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fnmaddbf16_v8bf_maskz, "__builtin_ia32_fnmaddbf16128_maskz", IX86_BUILTIN_FNMADDBF16128_MASKZ, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_fnmsubbf16_v32bf_mask, "__builtin_ia32_fnmsubbf16512_mask", IX86_BUILTIN_FNMSUBBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_fnmsubbf16_v32bf_mask3, "__builtin_ia32_fnmsubbf16512_mask3", IX86_BUILTIN_FNMSUBBF16512_MASK3, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_fnmsubbf16_v32bf_maskz, "__builtin_ia32_fnmsubbf16512_maskz", IX86_BUILTIN_FNMSUBBF16512_MASKZ, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fnmsubbf16_v16bf_mask, "__builtin_ia32_fnmsubbf16256_mask", IX86_BUILTIN_FNMSUBBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fnmsubbf16_v16bf_mask3, "__builtin_ia32_fnmsubbf16256_mask3", IX86_BUILTIN_FNMSUBBF16256_MASK3, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fnmsubbf16_v16bf_maskz, "__builtin_ia32_fnmsubbf16256_maskz", IX86_BUILTIN_FNMSUBBF16256_MASKZ, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fnmsubbf16_v8bf_mask, "__builtin_ia32_fnmsubbf16128_mask", IX86_BUILTIN_FNMSUBBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fnmsubbf16_v8bf_mask3, "__builtin_ia32_fnmsubbf16128_mask3", IX86_BUILTIN_FNMSUBBF16128_MASK3, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fnmsubbf16_v8bf_maskz, "__builtin_ia32_fnmsubbf16128_maskz", IX86_BUILTIN_FNMSUBBF16128_MASKZ, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_rsqrtbf16_v32bf_mask, "__builtin_ia32_rsqrtbf16512_mask", IX86_BUILTIN_RSQRTBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_rsqrtbf16_v16bf_mask, "__builtin_ia32_rsqrtbf16256_mask", IX86_BUILTIN_RSQRTBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_rsqrtbf16_v8bf_mask, "__builtin_ia32_rsqrtbf16128_mask", IX86_BUILTIN_RSQRTBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_sqrtbf16_v32bf_mask, "__builtin_ia32_sqrtbf16512_mask", IX86_BUILTIN_SQRTBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_sqrtbf16_v16bf_mask, "__builtin_ia32_sqrtbf16256_mask", IX86_BUILTIN_SQRTBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_sqrtbf16_v8bf_mask, "__builtin_ia32_sqrtbf16128_mask", IX86_BUILTIN_SQRTBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_rcpbf16_v32bf_mask, "__builtin_ia32_rcpbf16512_mask", IX86_BUILTIN_RCPBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_rcpbf16_v16bf_mask, "__builtin_ia32_rcpbf16256_mask", IX86_BUILTIN_RCPBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_rcpbf16_v8bf_mask, "__builtin_ia32_rcpbf16128_mask", IX86_BUILTIN_RCPBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_getexpbf16_v32bf_mask, "__builtin_ia32_getexpbf16512_mask", IX86_BUILTIN_GETEXPBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_getexpbf16_v16bf_mask, "__builtin_ia32_getexpbf16256_mask", IX86_BUILTIN_GETEXPBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_getexpbf16_v8bf_mask, "__builtin_ia32_getexpbf16128_mask", IX86_BUILTIN_GETEXPBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_rndscalebf16_v32bf_mask, "__builtin_ia32_rndscalebf16512_mask", IX86_BUILTIN_RNDSCALEBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_INT_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_rndscalebf16_v16bf_mask, "__builtin_ia32_rndscalebf16256_mask", IX86_BUILTIN_RNDSCALEBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_INT_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_rndscalebf16_v8bf_mask, "__builtin_ia32_rndscalebf16128_mask", IX86_BUILTIN_RNDSCALEBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_INT_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_reducebf16_v32bf_mask, "__builtin_ia32_reducebf16512_mask", IX86_BUILTIN_REDUCEBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_INT_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_reducebf16_v16bf_mask, "__builtin_ia32_reducebf16256_mask", IX86_BUILTIN_REDUCEBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_INT_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_reducebf16_v8bf_mask, "__builtin_ia32_reducebf16128_mask", IX86_BUILTIN_REDUCEBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_INT_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_getmantbf16_v32bf_mask, "__builtin_ia32_getmantbf16512_mask", IX86_BUILTIN_GETMANTBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_INT_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_getmantbf16_v16bf_mask, "__builtin_ia32_getmantbf16256_mask", IX86_BUILTIN_GETMANTBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_INT_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_getmantbf16_v8bf_mask, "__builtin_ia32_getmantbf16128_mask", IX86_BUILTIN_GETMANTBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_INT_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_fpclassbf16_v32bf_mask, "__builtin_ia32_fpclassbf16512_mask", IX86_BUILTIN_FPCLASSBF16512_MASK, UNKNOWN, (int) SI_FTYPE_V32BF_INT_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fpclassbf16_v16bf_mask, "__builtin_ia32_fpclassbf16256_mask", IX86_BUILTIN_FPCLASSBF16256_MASK, UNKNOWN, (int) HI_FTYPE_V16BF_INT_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_fpclassbf16_v8bf_mask, "__builtin_ia32_fpclassbf16128_mask", IX86_BUILTIN_FPCLASSBF16128_MASK, UNKNOWN, (int) QI_FTYPE_V8BF_INT_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cmpbf16_v32bf_mask, "__builtin_ia32_cmpbf16512_mask", IX86_BUILTIN_CMPBF16512_MASK, UNKNOWN, (int) USI_FTYPE_V32BF_V32BF_INT_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cmpbf16_v16bf_mask, "__builtin_ia32_cmpbf16256_mask", IX86_BUILTIN_CMPBF16256_MASK, UNKNOWN, (int) UHI_FTYPE_V16BF_V16BF_INT_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cmpbf16_v8bf_mask, "__builtin_ia32_cmpbf16128_mask", IX86_BUILTIN_CMPBF16128_MASK, UNKNOWN, (int) UQI_FTYPE_V8BF_V8BF_INT_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_comisbf16_v8bf, "__builtin_ia32_vcomisbf16eq", IX86_BUILTIN_VCOMISBF16EQ, EQ, (int) INT_FTYPE_V8BF_V8BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_comisbf16_v8bf, "__builtin_ia32_vcomisbf16gt", IX86_BUILTIN_VCOMISBF16GT, GT, (int) INT_FTYPE_V8BF_V8BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_comisbf16_v8bf, "__builtin_ia32_vcomisbf16ge", IX86_BUILTIN_VCOMISBF16GE, GE, (int) INT_FTYPE_V8BF_V8BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_comisbf16_v8bf, "__builtin_ia32_vcomisbf16le", IX86_BUILTIN_VCOMISBF16LE, LE, (int) INT_FTYPE_V8BF_V8BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_comisbf16_v8bf, "__builtin_ia32_vcomisbf16lt", IX86_BUILTIN_VCOMISBF16LT, LT, (int) INT_FTYPE_V8BF_V8BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_comisbf16_v8bf, "__builtin_ia32_vcomisbf16neq", IX86_BUILTIN_VCOMISBF16NE, NE, (int) INT_FTYPE_V8BF_V8BF)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvtbf162ibsv8bf_mask, "__builtin_ia32_cvtbf162ibs128_mask", IX86_BUILTIN_CVTBF162IBS128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8BF_V8HI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvtbf162ibsv16bf_mask, "__builtin_ia32_cvtbf162ibs256_mask", IX86_BUILTIN_CVTBF162IBS256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16BF_V16HI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvtbf162ibsv32bf_mask, "__builtin_ia32_cvtbf162ibs512_mask", IX86_BUILTIN_CVTBF162IBS512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32BF_V32HI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvtbf162iubsv8bf_mask, "__builtin_ia32_cvtbf162iubs128_mask", IX86_BUILTIN_CVTBF162IUBS128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8BF_V8HI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvtbf162iubsv16bf_mask, "__builtin_ia32_cvtbf162iubs256_mask", IX86_BUILTIN_CVTBF162IUBS256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16BF_V16HI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvtbf162iubsv32bf_mask, "__builtin_ia32_cvtbf162iubs512_mask", IX86_BUILTIN_CVTBF162IUBS512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32BF_V32HI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvtph2ibsv8hf_mask, "__builtin_ia32_cvtph2ibs128_mask", IX86_BUILTIN_CVTPH2IBS128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HF_V8HI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvtph2ibsv16hf_mask, "__builtin_ia32_cvtph2ibs256_mask", IX86_BUILTIN_CVTPH2IBS256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HF_V16HI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvtph2ibsv32hf_mask, "__builtin_ia32_cvtph2ibs512_mask", IX86_BUILTIN_CVTPH2IBS512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvtph2iubsv8hf_mask, "__builtin_ia32_cvtph2iubs128_mask", IX86_BUILTIN_CVTPH2IUBS128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HF_V8HI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvtph2iubsv16hf_mask, "__builtin_ia32_cvtph2iubs256_mask", IX86_BUILTIN_CVTPH2IUBS256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HF_V16HI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvtph2iubsv32hf_mask, "__builtin_ia32_cvtph2iubs512_mask", IX86_BUILTIN_CVTPH2IUBS512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvtps2ibsv4sf_mask, "__builtin_ia32_cvtps2ibs128_mask", IX86_BUILTIN_CVTPS2IBS128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvtps2ibsv8sf_mask, "__builtin_ia32_cvtps2ibs256_mask", IX86_BUILTIN_CVTPS2IBS256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvtps2ibsv16sf_mask, "__builtin_ia32_cvtps2ibs512_mask", IX86_BUILTIN_CVTPS2IBS512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvtps2iubsv4sf_mask, "__builtin_ia32_cvtps2iubs128_mask", IX86_BUILTIN_CVTPS2IUBS128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvtps2iubsv8sf_mask, "__builtin_ia32_cvtps2iubs256_mask", IX86_BUILTIN_CVTPS2IUBS256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvtps2iubsv16sf_mask, "__builtin_ia32_cvtps2iubs512_mask", IX86_BUILTIN_CVTPS2IUBS512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvttbf162ibsv8bf_mask, "__builtin_ia32_cvttbf162ibs128_mask", IX86_BUILTIN_CVTTBF162IBS128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8BF_V8HI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvttbf162ibsv16bf_mask, "__builtin_ia32_cvttbf162ibs256_mask", IX86_BUILTIN_CVTTBF162IBS256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16BF_V16HI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvttbf162ibsv32bf_mask, "__builtin_ia32_cvttbf162ibs512_mask", IX86_BUILTIN_CVTTBF162IBS512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32BF_V32HI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvttbf162iubsv8bf_mask, "__builtin_ia32_cvttbf162iubs128_mask", IX86_BUILTIN_CVTTBF162IUBS128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8BF_V8HI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvttbf162iubsv16bf_mask, "__builtin_ia32_cvttbf162iubs256_mask", IX86_BUILTIN_CVTTBF162IUBS256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16BF_V16HI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvttbf162iubsv32bf_mask, "__builtin_ia32_cvttbf162iubs512_mask", IX86_BUILTIN_CVTTBF162IUBS512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32BF_V32HI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvttph2ibsv8hf_mask, "__builtin_ia32_cvttph2ibs128_mask", IX86_BUILTIN_CVTTPH2IBS128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HF_V8HI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvttph2ibsv16hf_mask, "__builtin_ia32_cvttph2ibs256_mask", IX86_BUILTIN_CVTTPH2IBS256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HF_V16HI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvttph2ibsv32hf_mask, "__builtin_ia32_cvttph2ibs512_mask", IX86_BUILTIN_CVTTPH2IBS512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvttph2iubsv8hf_mask, "__builtin_ia32_cvttph2iubs128_mask", IX86_BUILTIN_CVTTPH2IUBS128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HF_V8HI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvttph2iubsv16hf_mask, "__builtin_ia32_cvttph2iubs256_mask", IX86_BUILTIN_CVTTPH2IUBS256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HF_V16HI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvttph2iubsv32hf_mask, "__builtin_ia32_cvttph2iubs512_mask", IX86_BUILTIN_CVTTPH2IUBS512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvttps2ibsv4sf_mask, "__builtin_ia32_cvttps2ibs128_mask", IX86_BUILTIN_CVTTPS2IBS128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvttps2ibsv8sf_mask, "__builtin_ia32_cvttps2ibs256_mask", IX86_BUILTIN_CVTTPS2IBS256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvttps2ibsv16sf_mask, "__builtin_ia32_cvttps2ibs512_mask", IX86_BUILTIN_CVTTPS2IBS512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvttps2iubsv4sf_mask, "__builtin_ia32_cvttps2iubs128_mask", IX86_BUILTIN_CVTTPS2IUBS128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_cvttps2iubsv8sf_mask, "__builtin_ia32_cvttps2iubs256_mask", IX86_BUILTIN_CVTTPS2IUBS256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvttps2iubsv16sf_mask, "__builtin_ia32_cvttps2iubs512_mask", IX86_BUILTIN_CVTTPS2IUBS512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttpd2dqsv2df_mask, "__builtin_ia32_cvttpd2dqs128_mask", IX86_BUILTIN_VCVTTPD2DQS128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttpd2dqsv4df_mask, "__builtin_ia32_cvttpd2dqs256_mask", IX86_BUILTIN_VCVTTPD2DQS256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vcvttpd2dqsv8df_mask, "__builtin_ia32_cvttpd2dqs512_mask", IX86_BUILTIN_VCVTTPD2DQS512_MASK, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttpd2qqsv2df_mask, "__builtin_ia32_cvttpd2qqs128_mask", IX86_BUILTIN_VCVTTPD2QQS128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttpd2qqsv4df_mask, "__builtin_ia32_cvttpd2qqs256_mask", IX86_BUILTIN_VCVTTPD2QQS256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vcvttpd2qqsv8df_mask, "__builtin_ia32_cvttpd2qqs512_mask", IX86_BUILTIN_VCVTTPD2QQS512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttpd2udqsv2df_mask, "__builtin_ia32_cvttpd2udqs128_mask", IX86_BUILTIN_VCVTTPD2UDQS128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttpd2udqsv4df_mask, "__builtin_ia32_cvttpd2udqs256_mask", IX86_BUILTIN_VCVTTPD2UDQS256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vcvttpd2udqsv8df_mask, "__builtin_ia32_cvttpd2udqs512_mask", IX86_BUILTIN_VCVTTPD2UDQS512_MASK, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttpd2uqqsv2df_mask, "__builtin_ia32_cvttpd2uqqs128_mask", IX86_BUILTIN_VCVTTPD2UQQS128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttpd2uqqsv4df_mask, "__builtin_ia32_cvttpd2uqqs256_mask", IX86_BUILTIN_VCVTTPD2UQQS256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vcvttpd2uqqsv8df_mask, "__builtin_ia32_cvttpd2uqqs512_mask", IX86_BUILTIN_VCVTTPD2UQQS512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttps2dqsv4sf_mask, "__builtin_ia32_cvttps2dqs128_mask", IX86_BUILTIN_VCVTTPS2DQS128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttps2dqsv8sf_mask, "__builtin_ia32_cvttps2dqs256_mask", IX86_BUILTIN_VCVTTPS2DQS256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vcvttps2dqsv16sf_mask, "__builtin_ia32_cvttps2dqs512_mask", IX86_BUILTIN_VCVTTPS2DQS512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttps2qqsv2di_mask, "__builtin_ia32_cvttps2qqs128_mask", IX86_BUILTIN_VCVTTPS2QQS128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttps2qqsv4di_mask, "__builtin_ia32_cvttps2qqs256_mask", IX86_BUILTIN_VCVTTPS2QQS256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vcvttps2qqsv8di_mask, "__builtin_ia32_cvttps2qqs512_mask", IX86_BUILTIN_VCVTTPS2QQS512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttps2udqsv4sf_mask, "__builtin_ia32_cvttps2udqs128_mask", IX86_BUILTIN_VCVTTPS2UDQS128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttps2udqsv8sf_mask, "__builtin_ia32_cvttps2udqs256_mask", IX86_BUILTIN_VCVTTPS2UDQS256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vcvttps2udqsv16sf_mask, "__builtin_ia32_cvttps2udqs512_mask", IX86_BUILTIN_VCVTTPS2UDQS512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttps2uqqsv2di_mask, "__builtin_ia32_cvttps2uqqs128_mask", IX86_BUILTIN_VCVTTPS2UQQS128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttps2uqqsv4di_mask, "__builtin_ia32_cvttps2uqqs256_mask", IX86_BUILTIN_VCVTTPS2UQQS256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vcvttps2uqqsv8di_mask, "__builtin_ia32_cvttps2uqqs512_mask", IX86_BUILTIN_VCVTTPS2UQQS512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_minmaxbf16_v8bf_mask, "__builtin_ia32_minmaxbf16128_mask", IX86_BUILTIN_MINMAXBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_INT_V8BF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_minmaxbf16_v16bf_mask, "__builtin_ia32_minmaxbf16256_mask", IX86_BUILTIN_MINMAXBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_INT_V16BF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_minmaxbf16_v32bf_mask, "__builtin_ia32_minmaxbf16512_mask", IX86_BUILTIN_MINMAXBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_INT_V32BF_USI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_minmaxpv4df_mask, "__builtin_ia32_minmaxpd256_mask", IX86_BUILTIN_MINMAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_minmaxpv16hf_mask, "__builtin_ia32_minmaxph256_mask", IX86_BUILTIN_MINMAXPH256_MASK, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_INT_V16HF_UHI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_minmaxpv8sf_mask, "__builtin_ia32_minmaxps256_mask", IX86_BUILTIN_MINMAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_minmaxpv2df_mask, "__builtin_ia32_minmaxpd128_mask", IX86_BUILTIN_MINMAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_minmaxpv8hf_mask, "__builtin_ia32_minmaxph128_mask", IX86_BUILTIN_MINMAXPH128_MASK, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_INT_V8HF_UQI)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_minmaxpv4sf_mask, "__builtin_ia32_minmaxps128_mask", IX86_BUILTIN_MINMAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssd_v16si, "__builtin_ia32_vpdpbssd512", IX86_BUILTIN_VPDPBSSDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssds_v16si, "__builtin_ia32_vpdpbssds512", IX86_BUILTIN_VPDPBSSDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsud_v16si, "__builtin_ia32_vpdpbsud512", IX86_BUILTIN_VPDPBSUDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsuds_v16si, "__builtin_ia32_vpdpbsuds512", IX86_BUILTIN_VPDPBSUDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuud_v16si, "__builtin_ia32_vpdpbuud512", IX86_BUILTIN_VPDPBUUDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuuds_v16si, "__builtin_ia32_vpdpbuuds512", IX86_BUILTIN_VPDPBUUDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssd_v16si_mask, "__builtin_ia32_vpdpbssd_v16si_mask", IX86_BUILTIN_VPDPBSSDV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssd_v16si_maskz, "__builtin_ia32_vpdpbssd_v16si_maskz", IX86_BUILTIN_VPDPBSSDV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssds_v16si_mask, "__builtin_ia32_vpdpbssds_v16si_mask", IX86_BUILTIN_VPDPBSSDSV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssds_v16si_maskz, "__builtin_ia32_vpdpbssds_v16si_maskz", IX86_BUILTIN_VPDPBSSDSV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsud_v16si_mask, "__builtin_ia32_vpdpbsud_v16si_mask", IX86_BUILTIN_VPDPBSUDV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsud_v16si_maskz, "__builtin_ia32_vpdpbsud_v16si_maskz", IX86_BUILTIN_VPDPBSUDV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsuds_v16si_mask, "__builtin_ia32_vpdpbsuds_v16si_mask", IX86_BUILTIN_VPDPBSUDSV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsuds_v16si_maskz, "__builtin_ia32_vpdpbsuds_v16si_maskz", IX86_BUILTIN_VPDPBSUDSV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuud_v16si_mask, "__builtin_ia32_vpdpbuud_v16si_mask", IX86_BUILTIN_VPDPBUUDV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuud_v16si_maskz, "__builtin_ia32_vpdpbuud_v16si_maskz", IX86_BUILTIN_VPDPBUUDV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuuds_v16si_mask, "__builtin_ia32_vpdpbuuds_v16si_mask", IX86_BUILTIN_VPDPBUUDSV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuuds_v16si_maskz, "__builtin_ia32_vpdpbuuds_v16si_maskz", IX86_BUILTIN_VPDPBUUDSV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssd_v8si_mask, "__builtin_ia32_vpdpbssd_v8si_mask", IX86_BUILTIN_VPDPBSSDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssd_v8si_maskz, "__builtin_ia32_vpdpbssd_v8si_maskz", IX86_BUILTIN_VPDPBSSDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssds_v8si_mask, "__builtin_ia32_vpdpbssds_v8si_mask", IX86_BUILTIN_VPDPBSSDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssds_v8si_maskz, "__builtin_ia32_vpdpbssds_v8si_maskz", IX86_BUILTIN_VPDPBSSDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsud_v8si_mask, "__builtin_ia32_vpdpbsud_v8si_mask", IX86_BUILTIN_VPDPBSUDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsud_v8si_maskz, "__builtin_ia32_vpdpbsud_v8si_maskz", IX86_BUILTIN_VPDPBSUDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsuds_v8si_mask, "__builtin_ia32_vpdpbsuds_v8si_mask", IX86_BUILTIN_VPDPBSUDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsuds_v8si_maskz, "__builtin_ia32_vpdpbsuds_v8si_maskz", IX86_BUILTIN_VPDPBSUDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuud_v8si_mask, "__builtin_ia32_vpdpbuud_v8si_mask", IX86_BUILTIN_VPDPBUUDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuud_v8si_maskz, "__builtin_ia32_vpdpbuud_v8si_maskz", IX86_BUILTIN_VPDPBUUDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuuds_v8si_mask, "__builtin_ia32_vpdpbuuds_v8si_mask", IX86_BUILTIN_VPDPBUUDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuuds_v8si_maskz, "__builtin_ia32_vpdpbuuds_v8si_maskz", IX86_BUILTIN_VPDPBUUDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssd_v4si_mask, "__builtin_ia32_vpdpbssd_v4si_mask", IX86_BUILTIN_VPDPBSSDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssd_v4si_maskz, "__builtin_ia32_vpdpbssd_v4si_maskz", IX86_BUILTIN_VPDPBSSDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssds_v4si_mask, "__builtin_ia32_vpdpbssds_v4si_mask", IX86_BUILTIN_VPDPBSSDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbssds_v4si_maskz, "__builtin_ia32_vpdpbssds_v4si_maskz", IX86_BUILTIN_VPDPBSSDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsud_v4si_mask, "__builtin_ia32_vpdpbsud_v4si_mask", IX86_BUILTIN_VPDPBSUDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsud_v4si_maskz, "__builtin_ia32_vpdpbsud_v4si_maskz", IX86_BUILTIN_VPDPBSUDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsuds_v4si_mask, "__builtin_ia32_vpdpbsuds_v4si_mask", IX86_BUILTIN_VPDPBSUDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbsuds_v4si_maskz, "__builtin_ia32_vpdpbsuds_v4si_maskz", IX86_BUILTIN_VPDPBSUDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuud_v4si_mask, "__builtin_ia32_vpdpbuud_v4si_mask", IX86_BUILTIN_VPDPBUUDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuud_v4si_maskz, "__builtin_ia32_vpdpbuud_v4si_maskz", IX86_BUILTIN_VPDPBUUDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuuds_v4si_mask, "__builtin_ia32_vpdpbuuds_v4si_mask", IX86_BUILTIN_VPDPBUUDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpbuuds_v4si_maskz, "__builtin_ia32_vpdpbuuds_v4si_maskz", IX86_BUILTIN_VPDPBUUDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsud_v16si, "__builtin_ia32_vpdpwsud512", IX86_BUILTIN_VPDPWSUDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsuds_v16si, "__builtin_ia32_vpdpwsuds512", IX86_BUILTIN_VPDPWSUDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusd_v16si, "__builtin_ia32_vpdpwusd512", IX86_BUILTIN_VPDPWUSDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusds_v16si, "__builtin_ia32_vpdpwusds512", IX86_BUILTIN_VPDPWUSDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuud_v16si, "__builtin_ia32_vpdpwuud512", IX86_BUILTIN_VPDPWUUDV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuuds_v16si, "__builtin_ia32_vpdpwuuds512", IX86_BUILTIN_VPDPWUUDSV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsud_v16si_mask, "__builtin_ia32_vpdpwsud_v16si_mask", IX86_BUILTIN_VPDPWSUDV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsud_v16si_maskz, "__builtin_ia32_vpdpwsud_v16si_maskz", IX86_BUILTIN_VPDPWSUDV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsuds_v16si_mask, "__builtin_ia32_vpdpwsuds_v16si_mask", IX86_BUILTIN_VPDPWSUDSV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsuds_v16si_maskz, "__builtin_ia32_vpdpwsuds_v16si_maskz", IX86_BUILTIN_VPDPWSUDSV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusd_v16si_mask, "__builtin_ia32_vpdpwusd_v16si_mask", IX86_BUILTIN_VPDPWUSDV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusd_v16si_maskz, "__builtin_ia32_vpdpwusd_v16si_maskz", IX86_BUILTIN_VPDPWUSDV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusds_v16si_mask, "__builtin_ia32_vpdpwusds_v16si_mask", IX86_BUILTIN_VPDPWUSDSV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusds_v16si_maskz, "__builtin_ia32_vpdpwusds_v16si_maskz", IX86_BUILTIN_VPDPWUSDSV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuud_v16si_mask, "__builtin_ia32_vpdpwuud_v16si_mask", IX86_BUILTIN_VPDPWUUDV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuud_v16si_maskz, "__builtin_ia32_vpdpwuud_v16si_maskz", IX86_BUILTIN_VPDPWUUDV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuuds_v16si_mask, "__builtin_ia32_vpdpwuuds_v16si_mask", IX86_BUILTIN_VPDPWUUDSV16SI_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuuds_v16si_maskz, "__builtin_ia32_vpdpwuuds_v16si_maskz", IX86_BUILTIN_VPDPWUUDSV16SI_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsud_v8si_mask, "__builtin_ia32_vpdpwsud_v8si_mask", IX86_BUILTIN_VPDPWSUDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsud_v8si_maskz, "__builtin_ia32_vpdpwsud_v8si_maskz", IX86_BUILTIN_VPDPWSUDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsuds_v8si_mask, "__builtin_ia32_vpdpwsuds_v8si_mask", IX86_BUILTIN_VPDPWSUDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsuds_v8si_maskz, "__builtin_ia32_vpdpwsuds_v8si_maskz", IX86_BUILTIN_VPDPWSUDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusd_v8si_mask, "__builtin_ia32_vpdpwusd_v8si_mask", IX86_BUILTIN_VPDPWUSDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusd_v8si_maskz, "__builtin_ia32_vpdpwusd_v8si_maskz", IX86_BUILTIN_VPDPWUSDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusds_v8si_mask, "__builtin_ia32_vpdpwusds_v8si_mask", IX86_BUILTIN_VPDPWUSDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusds_v8si_maskz, "__builtin_ia32_vpdpwusds_v8si_maskz", IX86_BUILTIN_VPDPWUSDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuud_v8si_mask, "__builtin_ia32_vpdpwuud_v8si_mask", IX86_BUILTIN_VPDPWUUDV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuud_v8si_maskz, "__builtin_ia32_vpdpwuud_v8si_maskz", IX86_BUILTIN_VPDPWUUDV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuuds_v8si_mask, "__builtin_ia32_vpdpwuuds_v8si_mask", IX86_BUILTIN_VPDPWUUDSV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuuds_v8si_maskz, "__builtin_ia32_vpdpwuuds_v8si_maskz", IX86_BUILTIN_VPDPWUUDSV8SI_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsud_v4si_mask, "__builtin_ia32_vpdpwsud_v4si_mask", IX86_BUILTIN_VPDPWSUDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsud_v4si_maskz, "__builtin_ia32_vpdpwsud_v4si_maskz", IX86_BUILTIN_VPDPWSUDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsuds_v4si_mask, "__builtin_ia32_vpdpwsuds_v4si_mask", IX86_BUILTIN_VPDPWSUDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwsuds_v4si_maskz, "__builtin_ia32_vpdpwsuds_v4si_maskz", IX86_BUILTIN_VPDPWSUDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusd_v4si_mask, "__builtin_ia32_vpdpwusd_v4si_mask", IX86_BUILTIN_VPDPWUSDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusd_v4si_maskz, "__builtin_ia32_vpdpwusd_v4si_maskz", IX86_BUILTIN_VPDPWUSDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusds_v4si_mask, "__builtin_ia32_vpdpwusds_v4si_mask", IX86_BUILTIN_VPDPWUSDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwusds_v4si_maskz, "__builtin_ia32_vpdpwusds_v4si_maskz", IX86_BUILTIN_VPDPWUSDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuud_v4si_mask, "__builtin_ia32_vpdpwuud_v4si_mask", IX86_BUILTIN_VPDPWUUDV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuud_v4si_maskz, "__builtin_ia32_vpdpwuud_v4si_maskz", IX86_BUILTIN_VPDPWUUDV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuuds_v4si_mask, "__builtin_ia32_vpdpwuuds_v4si_mask", IX86_BUILTIN_VPDPWUUDSV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vpdpwuuds_v4si_maskz, "__builtin_ia32_vpdpwuuds_v4si_maskz", IX86_BUILTIN_VPDPWUUDSV4SI_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vdpphps_v16sf_mask, "__builtin_ia32_vdpphps512_mask", IX86_BUILTIN_VDPPHPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vdpphps_v16sf_maskz, "__builtin_ia32_vdpphps512_maskz", IX86_BUILTIN_VDPPHPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vdpphps_v8sf_mask, "__builtin_ia32_vdpphps256_mask", IX86_BUILTIN_VDPPHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vdpphps_v8sf_maskz, "__builtin_ia32_vdpphps256_maskz", IX86_BUILTIN_VDPPHPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vdpphps_v4sf_mask, "__builtin_ia32_vdpphps128_mask", IX86_BUILTIN_VDPPHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vdpphps_v4sf_maskz, "__builtin_ia32_vdpphps128_maskz", IX86_BUILTIN_VDPPHPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_mpsadbw, "__builtin_ia32_mpsadbw512", IX86_BUILTIN_AVX10_2_MPSADBW, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_mpsadbw_mask, "__builtin_ia32_mpsadbw512_mask", IX86_BUILTIN_VMPSADBW_V32HI_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx2_mpsadbw_mask, "__builtin_ia32_mpsadbw256_mask", IX86_BUILTIN_VMPSADBW_V16HI_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_sse4_1_mpsadbw_mask, "__builtin_ia32_mpsadbw128_mask", IX86_BUILTIN_VMPSADBW_V8HI_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvt2ps2phx_v16hf_mask, "__builtin_ia32_vcvt2ps2phx256_mask", IX86_BUILTIN_VCVT2PS2PHX_V16HF_MASK, UNKNOWN, (int) V16HF_FTYPE_V8SF_V8SF_V16HF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvt2ps2phx_v8hf_mask, "__builtin_ia32_vcvt2ps2phx128_mask", IX86_BUILTIN_VCVT2PS2PHX_V8HF_MASK, UNKNOWN, (int) V8HF_FTYPE_V4SF_V4SF_V8HF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2bf8v8hf, "__builtin_ia32_vcvtbiasph2bf8128", IX86_BUILTIN_VCVTBIASPH2BF8128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2bf8v8hf_mask, "__builtin_ia32_vcvtbiasph2bf8128_mask", IX86_BUILTIN_VCVTBIASPH2BF8128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2bf8v16hf_mask, "__builtin_ia32_vcvtbiasph2bf8256_mask", IX86_BUILTIN_VCVTBIASPH2BF8256_MASK, UNKNOWN, (int) V16QI_FTYPE_V32QI_V16HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2bf8v32hf_mask, "__builtin_ia32_vcvtbiasph2bf8512_mask", IX86_BUILTIN_VCVTBIASPH2BF8512_MASK, UNKNOWN, (int) V32QI_FTYPE_V64QI_V32HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2bf8sv8hf, "__builtin_ia32_vcvtbiasph2bf8s128", IX86_BUILTIN_VCVTBIASPH2BF8S128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2bf8sv8hf_mask, "__builtin_ia32_vcvtbiasph2bf8s128_mask", IX86_BUILTIN_VCVTBIASPH2BF8S128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2bf8sv16hf_mask, "__builtin_ia32_vcvtbiasph2bf8s256_mask", IX86_BUILTIN_VCVTBIASPH2BF8S256_MASK, UNKNOWN, (int) V16QI_FTYPE_V32QI_V16HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2bf8sv32hf_mask, "__builtin_ia32_vcvtbiasph2bf8s512_mask", IX86_BUILTIN_VCVTBIASPH2BF8S512_MASK, UNKNOWN, (int) V32QI_FTYPE_V64QI_V32HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2hf8v8hf, "__builtin_ia32_vcvtbiasph2hf8128", IX86_BUILTIN_VCVTBIASPH2HF8128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2hf8v8hf_mask, "__builtin_ia32_vcvtbiasph2hf8128_mask", IX86_BUILTIN_VCVTBIASPH2HF8128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2hf8v16hf_mask, "__builtin_ia32_vcvtbiasph2hf8256_mask", IX86_BUILTIN_VCVTBIASPH2HF8256_MASK, UNKNOWN, (int) V16QI_FTYPE_V32QI_V16HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2hf8v32hf_mask, "__builtin_ia32_vcvtbiasph2hf8512_mask", IX86_BUILTIN_VCVTBIASPH2HF8512_MASK, UNKNOWN, (int) V32QI_FTYPE_V64QI_V32HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2hf8sv8hf, "__builtin_ia32_vcvtbiasph2hf8s128", IX86_BUILTIN_VCVTBIASPH2HF8S128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2hf8sv8hf_mask, "__builtin_ia32_vcvtbiasph2hf8s128_mask", IX86_BUILTIN_VCVTBIASPH2HF8S128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V8HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2hf8sv16hf_mask, "__builtin_ia32_vcvtbiasph2hf8s256_mask", IX86_BUILTIN_VCVTBIASPH2HF8S256_MASK, UNKNOWN, (int) V16QI_FTYPE_V32QI_V16HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtbiasph2hf8sv32hf_mask, "__builtin_ia32_vcvtbiasph2hf8s512_mask", IX86_BUILTIN_VCVTBIASPH2HF8S512_MASK, UNKNOWN, (int) V32QI_FTYPE_V64QI_V32HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2bf8v8hf_mask, "__builtin_ia32_vcvt2ph2bf8128_mask", IX86_BUILTIN_VCVT2PH2BF8128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V8HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2bf8v16hf_mask, "__builtin_ia32_vcvt2ph2bf8256_mask", IX86_BUILTIN_VCVT2PH2BF8256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HF_V16HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2bf8v32hf_mask, "__builtin_ia32_vcvt2ph2bf8512_mask", IX86_BUILTIN_VCVT2PH2BF8512_MASK, UNKNOWN, (int) V64QI_FTYPE_V32HF_V32HF_V64QI_UDI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2bf8sv8hf_mask, "__builtin_ia32_vcvt2ph2bf8s128_mask", IX86_BUILTIN_VCVT2PH2BF8S128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V8HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2bf8sv16hf_mask, "__builtin_ia32_vcvt2ph2bf8s256_mask", IX86_BUILTIN_VCVT2PH2BF8S256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HF_V16HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2bf8sv32hf_mask, "__builtin_ia32_vcvt2ph2bf8s512_mask", IX86_BUILTIN_VCVT2PH2BF8S512_MASK, UNKNOWN, (int) V64QI_FTYPE_V32HF_V32HF_V64QI_UDI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2hf8v8hf_mask, "__builtin_ia32_vcvt2ph2hf8128_mask", IX86_BUILTIN_VCVT2PH2HF8128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V8HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2hf8v16hf_mask, "__builtin_ia32_vcvt2ph2hf8256_mask", IX86_BUILTIN_VCVT2PH2HF8256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HF_V16HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2hf8v32hf_mask, "__builtin_ia32_vcvt2ph2hf8512_mask", IX86_BUILTIN_VCVT2PH2HF8512_MASK, UNKNOWN, (int) V64QI_FTYPE_V32HF_V32HF_V64QI_UDI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2hf8sv8hf_mask, "__builtin_ia32_vcvt2ph2hf8s128_mask", IX86_BUILTIN_VCVT2PH2HF8S128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V8HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2hf8sv16hf_mask, "__builtin_ia32_vcvt2ph2hf8s256_mask", IX86_BUILTIN_VCVT2PH2HF8S256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HF_V16HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvt2ph2hf8sv32hf_mask, "__builtin_ia32_vcvt2ph2hf8s512_mask", IX86_BUILTIN_VCVT2PH2HF8S512_MASK, UNKNOWN, (int) V64QI_FTYPE_V32HF_V32HF_V64QI_UDI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2bf8v8hf_mask, "__builtin_ia32_vcvtph2bf8128_mask", IX86_BUILTIN_VCVTPH2BF8128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2bf8v16hf_mask, "__builtin_ia32_vcvtph2bf8256_mask", IX86_BUILTIN_VCVTPH2BF8256_MASK, UNKNOWN, (int) V16QI_FTYPE_V16HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2bf8v32hf_mask, "__builtin_ia32_vcvtph2bf8512_mask", IX86_BUILTIN_VCVTPH2BF8512_MASK, UNKNOWN, (int) V32QI_FTYPE_V32HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2bf8sv8hf_mask, "__builtin_ia32_vcvtph2bf8s128_mask", IX86_BUILTIN_VCVTPH2BF8S128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2bf8sv16hf_mask, "__builtin_ia32_vcvtph2bf8s256_mask", IX86_BUILTIN_VCVTPH2BF8S256_MASK, UNKNOWN, (int) V16QI_FTYPE_V16HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2bf8sv32hf_mask, "__builtin_ia32_vcvtph2bf8s512_mask", IX86_BUILTIN_VCVTPH2BF8S512_MASK, UNKNOWN, (int) V32QI_FTYPE_V32HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2hf8v8hf_mask, "__builtin_ia32_vcvtph2hf8128_mask", IX86_BUILTIN_VCVTPH2HF8128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2hf8v16hf_mask, "__builtin_ia32_vcvtph2hf8256_mask", IX86_BUILTIN_VCVTPH2HF8256_MASK, UNKNOWN, (int) V16QI_FTYPE_V16HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2hf8v32hf_mask, "__builtin_ia32_vcvtph2hf8512_mask", IX86_BUILTIN_VCVTPH2HF8512_MASK, UNKNOWN, (int) V32QI_FTYPE_V32HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2hf8sv8hf_mask, "__builtin_ia32_vcvtph2hf8s128_mask", IX86_BUILTIN_VCVTPH2HF8S128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2hf8sv16hf_mask, "__builtin_ia32_vcvtph2hf8s256_mask", IX86_BUILTIN_VCVTPH2HF8S256_MASK, UNKNOWN, (int) V16QI_FTYPE_V16HF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvtph2hf8sv32hf_mask, "__builtin_ia32_vcvtph2hf8s512_mask", IX86_BUILTIN_VCVTPH2HF8S512_MASK, UNKNOWN, (int) V32QI_FTYPE_V32HF_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvthf82phv8hf_mask, "__builtin_ia32_vcvthf82ph128_mask", IX86_BUILTIN_VCVTHF82PH128_MASK, UNKNOWN, (int) V8HF_FTYPE_V16QI_V8HF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvthf82phv16hf_mask, "__builtin_ia32_vcvthf82ph256_mask", IX86_BUILTIN_VCVTHF82PH256_MASK, UNKNOWN, (int) V16HF_FTYPE_V16QI_V16HF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_vcvthf82phv32hf_mask, "__builtin_ia32_vcvthf82ph512_mask", IX86_BUILTIN_VCVTHF82PH512_MASK, UNKNOWN, (int) V32HF_FTYPE_V32QI_V32HF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_addbf16_v32bf, "__builtin_ia32_addbf16512", IX86_BUILTIN_ADDBF16512, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_addbf16_v32bf_mask, "__builtin_ia32_addbf16512_mask", IX86_BUILTIN_ADDBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_addbf16_v16bf, "__builtin_ia32_addbf16256", IX86_BUILTIN_ADDBF16256, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_addbf16_v16bf_mask, "__builtin_ia32_addbf16256_mask", IX86_BUILTIN_ADDBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_addbf16_v8bf, "__builtin_ia32_addbf16128", IX86_BUILTIN_ADDBF16128, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_addbf16_v8bf_mask, "__builtin_ia32_addbf16128_mask", IX86_BUILTIN_ADDBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_subbf16_v32bf, "__builtin_ia32_subbf16512", IX86_BUILTIN_SUBBF16512, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_subbf16_v32bf_mask, "__builtin_ia32_subbf16512_mask", IX86_BUILTIN_SUBBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_subbf16_v16bf, "__builtin_ia32_subbf16256", IX86_BUILTIN_SUBBF16256, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_subbf16_v16bf_mask, "__builtin_ia32_subbf16256_mask", IX86_BUILTIN_SUBBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_subbf16_v8bf, "__builtin_ia32_subbf16128", IX86_BUILTIN_SUBBF16128, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_subbf16_v8bf_mask, "__builtin_ia32_subbf16128_mask", IX86_BUILTIN_SUBBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_mulbf16_v32bf, "__builtin_ia32_mulbf16512", IX86_BUILTIN_MULBF16512, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_mulbf16_v32bf_mask, "__builtin_ia32_mulbf16512_mask", IX86_BUILTIN_MULBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_mulbf16_v16bf, "__builtin_ia32_mulbf16256", IX86_BUILTIN_MULBF16256, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_mulbf16_v16bf_mask, "__builtin_ia32_mulbf16256_mask", IX86_BUILTIN_MULBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_mulbf16_v8bf, "__builtin_ia32_mulbf16128", IX86_BUILTIN_MULBF16128, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_mulbf16_v8bf_mask, "__builtin_ia32_mulbf16128_mask", IX86_BUILTIN_MULBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_divbf16_v32bf, "__builtin_ia32_divbf16512", IX86_BUILTIN_DIVBF16512, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_divbf16_v32bf_mask, "__builtin_ia32_divbf16512_mask", IX86_BUILTIN_DIVBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_divbf16_v16bf, "__builtin_ia32_divbf16256", IX86_BUILTIN_DIVBF16256, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_divbf16_v16bf_mask, "__builtin_ia32_divbf16256_mask", IX86_BUILTIN_DIVBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_divbf16_v8bf, "__builtin_ia32_divbf16128", IX86_BUILTIN_DIVBF16128, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_divbf16_v8bf_mask, "__builtin_ia32_divbf16128_mask", IX86_BUILTIN_DIVBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_smaxbf16_v32bf, "__builtin_ia32_maxbf16512", IX86_BUILTIN_MAXBF16512, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_smaxbf16_v32bf_mask, "__builtin_ia32_maxbf16512_mask", IX86_BUILTIN_MAXBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_smaxbf16_v16bf, "__builtin_ia32_maxbf16256", IX86_BUILTIN_MAXBF16256, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_smaxbf16_v16bf_mask, "__builtin_ia32_maxbf16256_mask", IX86_BUILTIN_MAXBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_smaxbf16_v8bf, "__builtin_ia32_maxbf16128", IX86_BUILTIN_MAXBF16128, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_smaxbf16_v8bf_mask, "__builtin_ia32_maxbf16128_mask", IX86_BUILTIN_MAXBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_sminbf16_v32bf, "__builtin_ia32_minbf16512", IX86_BUILTIN_MINBF16512, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_sminbf16_v32bf_mask, "__builtin_ia32_minbf16512_mask", IX86_BUILTIN_MINBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_sminbf16_v16bf, "__builtin_ia32_minbf16256", IX86_BUILTIN_MINBF16256, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_sminbf16_v16bf_mask, "__builtin_ia32_minbf16256_mask", IX86_BUILTIN_MINBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_sminbf16_v8bf, "__builtin_ia32_minbf16128", IX86_BUILTIN_MINBF16128, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_sminbf16_v8bf_mask, "__builtin_ia32_minbf16128_mask", IX86_BUILTIN_MINBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_scalefbf16_v32bf, "__builtin_ia32_scalefbf16512", IX86_BUILTIN_SCALEFBF16512, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_scalefbf16_v32bf_mask, "__builtin_ia32_scalefbf16512_mask", IX86_BUILTIN_SCALEFBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_scalefbf16_v16bf, "__builtin_ia32_scalefbf16256", IX86_BUILTIN_SCALEFBF16256, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_scalefbf16_v16bf_mask, "__builtin_ia32_scalefbf16256_mask", IX86_BUILTIN_SCALEFBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_scalefbf16_v8bf, "__builtin_ia32_scalefbf16128", IX86_BUILTIN_SCALEFBF16128, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_scalefbf16_v8bf_mask, "__builtin_ia32_scalefbf16128_mask", IX86_BUILTIN_SCALEFBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fmaddbf16_v32bf_mask, "__builtin_ia32_fmaddbf16512_mask", IX86_BUILTIN_FMADDBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fmaddbf16_v32bf_mask3, "__builtin_ia32_fmaddbf16512_mask3", IX86_BUILTIN_FMADDBF16512_MASK3, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fmaddbf16_v32bf_maskz, "__builtin_ia32_fmaddbf16512_maskz", IX86_BUILTIN_FMADDBF16512_MASKZ, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fmaddbf16_v16bf_mask, "__builtin_ia32_fmaddbf16256_mask", IX86_BUILTIN_FMADDBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fmaddbf16_v16bf_mask3, "__builtin_ia32_fmaddbf16256_mask3", IX86_BUILTIN_FMADDBF16256_MASK3, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fmaddbf16_v16bf_maskz, "__builtin_ia32_fmaddbf16256_maskz", IX86_BUILTIN_FMADDBF16256_MASKZ, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fmaddbf16_v8bf_mask, "__builtin_ia32_fmaddbf16128_mask", IX86_BUILTIN_FMADDBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fmaddbf16_v8bf_mask3, "__builtin_ia32_fmaddbf16128_mask3", IX86_BUILTIN_FMADDBF16128_MASK3, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fmaddbf16_v8bf_maskz, "__builtin_ia32_fmaddbf16128_maskz", IX86_BUILTIN_FMADDBF16128_MASKZ, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fmsubbf16_v32bf_mask, "__builtin_ia32_fmsubbf16512_mask", IX86_BUILTIN_FMSUBBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fmsubbf16_v32bf_mask3, "__builtin_ia32_fmsubbf16512_mask3", IX86_BUILTIN_FMSUBBF16512_MASK3, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fmsubbf16_v32bf_maskz, "__builtin_ia32_fmsubbf16512_maskz", IX86_BUILTIN_FMSUBBF16512_MASKZ, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fmsubbf16_v16bf_mask, "__builtin_ia32_fmsubbf16256_mask", IX86_BUILTIN_FMSUBBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fmsubbf16_v16bf_mask3, "__builtin_ia32_fmsubbf16256_mask3", IX86_BUILTIN_FMSUBBF16256_MASK3, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fmsubbf16_v16bf_maskz, "__builtin_ia32_fmsubbf16256_maskz", IX86_BUILTIN_FMSUBBF16256_MASKZ, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fmsubbf16_v8bf_mask, "__builtin_ia32_fmsubbf16128_mask", IX86_BUILTIN_FMSUBBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fmsubbf16_v8bf_mask3, "__builtin_ia32_fmsubbf16128_mask3", IX86_BUILTIN_FMSUBBF16128_MASK3, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fmsubbf16_v8bf_maskz, "__builtin_ia32_fmsubbf16128_maskz", IX86_BUILTIN_FMSUBBF16128_MASKZ, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fnmaddbf16_v32bf_mask, "__builtin_ia32_fnmaddbf16512_mask", IX86_BUILTIN_FNMADDBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fnmaddbf16_v32bf_mask3, "__builtin_ia32_fnmaddbf16512_mask3", IX86_BUILTIN_FNMADDBF16512_MASK3, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fnmaddbf16_v32bf_maskz, "__builtin_ia32_fnmaddbf16512_maskz", IX86_BUILTIN_FNMADDBF16512_MASKZ, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fnmaddbf16_v16bf_mask, "__builtin_ia32_fnmaddbf16256_mask", IX86_BUILTIN_FNMADDBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fnmaddbf16_v16bf_mask3, "__builtin_ia32_fnmaddbf16256_mask3", IX86_BUILTIN_FNMADDBF16256_MASK3, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fnmaddbf16_v16bf_maskz, "__builtin_ia32_fnmaddbf16256_maskz", IX86_BUILTIN_FNMADDBF16256_MASKZ, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fnmaddbf16_v8bf_mask, "__builtin_ia32_fnmaddbf16128_mask", IX86_BUILTIN_FNMADDBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fnmaddbf16_v8bf_mask3, "__builtin_ia32_fnmaddbf16128_mask3", IX86_BUILTIN_FNMADDBF16128_MASK3, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fnmaddbf16_v8bf_maskz, "__builtin_ia32_fnmaddbf16128_maskz", IX86_BUILTIN_FNMADDBF16128_MASKZ, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fnmsubbf16_v32bf_mask, "__builtin_ia32_fnmsubbf16512_mask", IX86_BUILTIN_FNMSUBBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fnmsubbf16_v32bf_mask3, "__builtin_ia32_fnmsubbf16512_mask3", IX86_BUILTIN_FNMSUBBF16512_MASK3, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fnmsubbf16_v32bf_maskz, "__builtin_ia32_fnmsubbf16512_maskz", IX86_BUILTIN_FNMSUBBF16512_MASKZ, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fnmsubbf16_v16bf_mask, "__builtin_ia32_fnmsubbf16256_mask", IX86_BUILTIN_FNMSUBBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fnmsubbf16_v16bf_mask3, "__builtin_ia32_fnmsubbf16256_mask3", IX86_BUILTIN_FNMSUBBF16256_MASK3, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fnmsubbf16_v16bf_maskz, "__builtin_ia32_fnmsubbf16256_maskz", IX86_BUILTIN_FNMSUBBF16256_MASKZ, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fnmsubbf16_v8bf_mask, "__builtin_ia32_fnmsubbf16128_mask", IX86_BUILTIN_FNMSUBBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fnmsubbf16_v8bf_mask3, "__builtin_ia32_fnmsubbf16128_mask3", IX86_BUILTIN_FNMSUBBF16128_MASK3, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fnmsubbf16_v8bf_maskz, "__builtin_ia32_fnmsubbf16128_maskz", IX86_BUILTIN_FNMSUBBF16128_MASKZ, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_rsqrtbf16_v32bf_mask, "__builtin_ia32_rsqrtbf16512_mask", IX86_BUILTIN_RSQRTBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_rsqrtbf16_v16bf_mask, "__builtin_ia32_rsqrtbf16256_mask", IX86_BUILTIN_RSQRTBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_rsqrtbf16_v8bf_mask, "__builtin_ia32_rsqrtbf16128_mask", IX86_BUILTIN_RSQRTBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_sqrtbf16_v32bf_mask, "__builtin_ia32_sqrtbf16512_mask", IX86_BUILTIN_SQRTBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_sqrtbf16_v16bf_mask, "__builtin_ia32_sqrtbf16256_mask", IX86_BUILTIN_SQRTBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_sqrtbf16_v8bf_mask, "__builtin_ia32_sqrtbf16128_mask", IX86_BUILTIN_SQRTBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_rcpbf16_v32bf_mask, "__builtin_ia32_rcpbf16512_mask", IX86_BUILTIN_RCPBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_rcpbf16_v16bf_mask, "__builtin_ia32_rcpbf16256_mask", IX86_BUILTIN_RCPBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_rcpbf16_v8bf_mask, "__builtin_ia32_rcpbf16128_mask", IX86_BUILTIN_RCPBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_getexpbf16_v32bf_mask, "__builtin_ia32_getexpbf16512_mask", IX86_BUILTIN_GETEXPBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_getexpbf16_v16bf_mask, "__builtin_ia32_getexpbf16256_mask", IX86_BUILTIN_GETEXPBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_getexpbf16_v8bf_mask, "__builtin_ia32_getexpbf16128_mask", IX86_BUILTIN_GETEXPBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_rndscalebf16_v32bf_mask, "__builtin_ia32_rndscalebf16512_mask", IX86_BUILTIN_RNDSCALEBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_INT_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_rndscalebf16_v16bf_mask, "__builtin_ia32_rndscalebf16256_mask", IX86_BUILTIN_RNDSCALEBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_INT_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_rndscalebf16_v8bf_mask, "__builtin_ia32_rndscalebf16128_mask", IX86_BUILTIN_RNDSCALEBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_INT_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_reducebf16_v32bf_mask, "__builtin_ia32_reducebf16512_mask", IX86_BUILTIN_REDUCEBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_INT_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_reducebf16_v16bf_mask, "__builtin_ia32_reducebf16256_mask", IX86_BUILTIN_REDUCEBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_INT_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_reducebf16_v8bf_mask, "__builtin_ia32_reducebf16128_mask", IX86_BUILTIN_REDUCEBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_INT_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_getmantbf16_v32bf_mask, "__builtin_ia32_getmantbf16512_mask", IX86_BUILTIN_GETMANTBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_INT_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_getmantbf16_v16bf_mask, "__builtin_ia32_getmantbf16256_mask", IX86_BUILTIN_GETMANTBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_INT_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_getmantbf16_v8bf_mask, "__builtin_ia32_getmantbf16128_mask", IX86_BUILTIN_GETMANTBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_INT_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fpclassbf16_v32bf_mask, "__builtin_ia32_fpclassbf16512_mask", IX86_BUILTIN_FPCLASSBF16512_MASK, UNKNOWN, (int) SI_FTYPE_V32BF_INT_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fpclassbf16_v16bf_mask, "__builtin_ia32_fpclassbf16256_mask", IX86_BUILTIN_FPCLASSBF16256_MASK, UNKNOWN, (int) HI_FTYPE_V16BF_INT_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_fpclassbf16_v8bf_mask, "__builtin_ia32_fpclassbf16128_mask", IX86_BUILTIN_FPCLASSBF16128_MASK, UNKNOWN, (int) QI_FTYPE_V8BF_INT_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cmpbf16_v32bf_mask, "__builtin_ia32_cmpbf16512_mask", IX86_BUILTIN_CMPBF16512_MASK, UNKNOWN, (int) USI_FTYPE_V32BF_V32BF_INT_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cmpbf16_v16bf_mask, "__builtin_ia32_cmpbf16256_mask", IX86_BUILTIN_CMPBF16256_MASK, UNKNOWN, (int) UHI_FTYPE_V16BF_V16BF_INT_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cmpbf16_v8bf_mask, "__builtin_ia32_cmpbf16128_mask", IX86_BUILTIN_CMPBF16128_MASK, UNKNOWN, (int) UQI_FTYPE_V8BF_V8BF_INT_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_comisbf16_v8bf, "__builtin_ia32_vcomisbf16eq", IX86_BUILTIN_VCOMISBF16EQ, EQ, (int) INT_FTYPE_V8BF_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_comisbf16_v8bf, "__builtin_ia32_vcomisbf16gt", IX86_BUILTIN_VCOMISBF16GT, GT, (int) INT_FTYPE_V8BF_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_comisbf16_v8bf, "__builtin_ia32_vcomisbf16ge", IX86_BUILTIN_VCOMISBF16GE, GE, (int) INT_FTYPE_V8BF_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_comisbf16_v8bf, "__builtin_ia32_vcomisbf16le", IX86_BUILTIN_VCOMISBF16LE, LE, (int) INT_FTYPE_V8BF_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_comisbf16_v8bf, "__builtin_ia32_vcomisbf16lt", IX86_BUILTIN_VCOMISBF16LT, LT, (int) INT_FTYPE_V8BF_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_comisbf16_v8bf, "__builtin_ia32_vcomisbf16neq", IX86_BUILTIN_VCOMISBF16NE, NE, (int) INT_FTYPE_V8BF_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtbf162ibsv8bf_mask, "__builtin_ia32_cvtbf162ibs128_mask", IX86_BUILTIN_CVTBF162IBS128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8BF_V8HI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtbf162ibsv16bf_mask, "__builtin_ia32_cvtbf162ibs256_mask", IX86_BUILTIN_CVTBF162IBS256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16BF_V16HI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtbf162ibsv32bf_mask, "__builtin_ia32_cvtbf162ibs512_mask", IX86_BUILTIN_CVTBF162IBS512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32BF_V32HI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtbf162iubsv8bf_mask, "__builtin_ia32_cvtbf162iubs128_mask", IX86_BUILTIN_CVTBF162IUBS128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8BF_V8HI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtbf162iubsv16bf_mask, "__builtin_ia32_cvtbf162iubs256_mask", IX86_BUILTIN_CVTBF162IUBS256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16BF_V16HI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtbf162iubsv32bf_mask, "__builtin_ia32_cvtbf162iubs512_mask", IX86_BUILTIN_CVTBF162IUBS512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32BF_V32HI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtph2ibsv8hf_mask, "__builtin_ia32_cvtph2ibs128_mask", IX86_BUILTIN_CVTPH2IBS128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HF_V8HI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtph2ibsv16hf_mask, "__builtin_ia32_cvtph2ibs256_mask", IX86_BUILTIN_CVTPH2IBS256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HF_V16HI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtph2ibsv32hf_mask, "__builtin_ia32_cvtph2ibs512_mask", IX86_BUILTIN_CVTPH2IBS512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtph2iubsv8hf_mask, "__builtin_ia32_cvtph2iubs128_mask", IX86_BUILTIN_CVTPH2IUBS128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HF_V8HI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtph2iubsv16hf_mask, "__builtin_ia32_cvtph2iubs256_mask", IX86_BUILTIN_CVTPH2IUBS256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HF_V16HI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtph2iubsv32hf_mask, "__builtin_ia32_cvtph2iubs512_mask", IX86_BUILTIN_CVTPH2IUBS512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtps2ibsv4sf_mask, "__builtin_ia32_cvtps2ibs128_mask", IX86_BUILTIN_CVTPS2IBS128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtps2ibsv8sf_mask, "__builtin_ia32_cvtps2ibs256_mask", IX86_BUILTIN_CVTPS2IBS256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtps2ibsv16sf_mask, "__builtin_ia32_cvtps2ibs512_mask", IX86_BUILTIN_CVTPS2IBS512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtps2iubsv4sf_mask, "__builtin_ia32_cvtps2iubs128_mask", IX86_BUILTIN_CVTPS2IUBS128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtps2iubsv8sf_mask, "__builtin_ia32_cvtps2iubs256_mask", IX86_BUILTIN_CVTPS2IUBS256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtps2iubsv16sf_mask, "__builtin_ia32_cvtps2iubs512_mask", IX86_BUILTIN_CVTPS2IUBS512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttbf162ibsv8bf_mask, "__builtin_ia32_cvttbf162ibs128_mask", IX86_BUILTIN_CVTTBF162IBS128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8BF_V8HI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttbf162ibsv16bf_mask, "__builtin_ia32_cvttbf162ibs256_mask", IX86_BUILTIN_CVTTBF162IBS256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16BF_V16HI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttbf162ibsv32bf_mask, "__builtin_ia32_cvttbf162ibs512_mask", IX86_BUILTIN_CVTTBF162IBS512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32BF_V32HI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttbf162iubsv8bf_mask, "__builtin_ia32_cvttbf162iubs128_mask", IX86_BUILTIN_CVTTBF162IUBS128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8BF_V8HI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttbf162iubsv16bf_mask, "__builtin_ia32_cvttbf162iubs256_mask", IX86_BUILTIN_CVTTBF162IUBS256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16BF_V16HI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttbf162iubsv32bf_mask, "__builtin_ia32_cvttbf162iubs512_mask", IX86_BUILTIN_CVTTBF162IUBS512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32BF_V32HI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttph2ibsv8hf_mask, "__builtin_ia32_cvttph2ibs128_mask", IX86_BUILTIN_CVTTPH2IBS128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HF_V8HI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttph2ibsv16hf_mask, "__builtin_ia32_cvttph2ibs256_mask", IX86_BUILTIN_CVTTPH2IBS256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HF_V16HI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttph2ibsv32hf_mask, "__builtin_ia32_cvttph2ibs512_mask", IX86_BUILTIN_CVTTPH2IBS512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttph2iubsv8hf_mask, "__builtin_ia32_cvttph2iubs128_mask", IX86_BUILTIN_CVTTPH2IUBS128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HF_V8HI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttph2iubsv16hf_mask, "__builtin_ia32_cvttph2iubs256_mask", IX86_BUILTIN_CVTTPH2IUBS256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HF_V16HI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttph2iubsv32hf_mask, "__builtin_ia32_cvttph2iubs512_mask", IX86_BUILTIN_CVTTPH2IUBS512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttps2ibsv4sf_mask, "__builtin_ia32_cvttps2ibs128_mask", IX86_BUILTIN_CVTTPS2IBS128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttps2ibsv8sf_mask, "__builtin_ia32_cvttps2ibs256_mask", IX86_BUILTIN_CVTTPS2IBS256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttps2ibsv16sf_mask, "__builtin_ia32_cvttps2ibs512_mask", IX86_BUILTIN_CVTTPS2IBS512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttps2iubsv4sf_mask, "__builtin_ia32_cvttps2iubs128_mask", IX86_BUILTIN_CVTTPS2IUBS128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttps2iubsv8sf_mask, "__builtin_ia32_cvttps2iubs256_mask", IX86_BUILTIN_CVTTPS2IUBS256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttps2iubsv16sf_mask, "__builtin_ia32_cvttps2iubs512_mask", IX86_BUILTIN_CVTTPS2IUBS512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttpd2dqsv2df_mask, "__builtin_ia32_cvttpd2dqs128_mask", IX86_BUILTIN_VCVTTPD2DQS128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttpd2dqsv4df_mask, "__builtin_ia32_cvttpd2dqs256_mask", IX86_BUILTIN_VCVTTPD2DQS256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttpd2dqsv8df_mask, "__builtin_ia32_cvttpd2dqs512_mask", IX86_BUILTIN_VCVTTPD2DQS512_MASK, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttpd2qqsv2df_mask, "__builtin_ia32_cvttpd2qqs128_mask", IX86_BUILTIN_VCVTTPD2QQS128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttpd2qqsv4df_mask, "__builtin_ia32_cvttpd2qqs256_mask", IX86_BUILTIN_VCVTTPD2QQS256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttpd2qqsv8df_mask, "__builtin_ia32_cvttpd2qqs512_mask", IX86_BUILTIN_VCVTTPD2QQS512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttpd2udqsv2df_mask, "__builtin_ia32_cvttpd2udqs128_mask", IX86_BUILTIN_VCVTTPD2UDQS128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttpd2udqsv4df_mask, "__builtin_ia32_cvttpd2udqs256_mask", IX86_BUILTIN_VCVTTPD2UDQS256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttpd2udqsv8df_mask, "__builtin_ia32_cvttpd2udqs512_mask", IX86_BUILTIN_VCVTTPD2UDQS512_MASK, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttpd2uqqsv2df_mask, "__builtin_ia32_cvttpd2uqqs128_mask", IX86_BUILTIN_VCVTTPD2UQQS128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttpd2uqqsv4df_mask, "__builtin_ia32_cvttpd2uqqs256_mask", IX86_BUILTIN_VCVTTPD2UQQS256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttpd2uqqsv8df_mask, "__builtin_ia32_cvttpd2uqqs512_mask", IX86_BUILTIN_VCVTTPD2UQQS512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttps2dqsv4sf_mask, "__builtin_ia32_cvttps2dqs128_mask", IX86_BUILTIN_VCVTTPS2DQS128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttps2dqsv8sf_mask, "__builtin_ia32_cvttps2dqs256_mask", IX86_BUILTIN_VCVTTPS2DQS256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttps2dqsv16sf_mask, "__builtin_ia32_cvttps2dqs512_mask", IX86_BUILTIN_VCVTTPS2DQS512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttps2qqsv2di_mask, "__builtin_ia32_cvttps2qqs128_mask", IX86_BUILTIN_VCVTTPS2QQS128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttps2qqsv4di_mask, "__builtin_ia32_cvttps2qqs256_mask", IX86_BUILTIN_VCVTTPS2QQS256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttps2qqsv8di_mask, "__builtin_ia32_cvttps2qqs512_mask", IX86_BUILTIN_VCVTTPS2QQS512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttps2udqsv4sf_mask, "__builtin_ia32_cvttps2udqs128_mask", IX86_BUILTIN_VCVTTPS2UDQS128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttps2udqsv8sf_mask, "__builtin_ia32_cvttps2udqs256_mask", IX86_BUILTIN_VCVTTPS2UDQS256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttps2udqsv16sf_mask, "__builtin_ia32_cvttps2udqs512_mask", IX86_BUILTIN_VCVTTPS2UDQS512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttps2uqqsv2di_mask, "__builtin_ia32_cvttps2uqqs128_mask", IX86_BUILTIN_VCVTTPS2UQQS128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttps2uqqsv4di_mask, "__builtin_ia32_cvttps2uqqs256_mask", IX86_BUILTIN_VCVTTPS2UQQS256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttps2uqqsv8di_mask, "__builtin_ia32_cvttps2uqqs512_mask", IX86_BUILTIN_VCVTTPS2UQQS512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_minmaxbf16_v8bf_mask, "__builtin_ia32_minmaxbf16128_mask", IX86_BUILTIN_MINMAXBF16128_MASK, UNKNOWN, (int) V8BF_FTYPE_V8BF_V8BF_INT_V8BF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_minmaxbf16_v16bf_mask, "__builtin_ia32_minmaxbf16256_mask", IX86_BUILTIN_MINMAXBF16256_MASK, UNKNOWN, (int) V16BF_FTYPE_V16BF_V16BF_INT_V16BF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_minmaxbf16_v32bf_mask, "__builtin_ia32_minmaxbf16512_mask", IX86_BUILTIN_MINMAXBF16512_MASK, UNKNOWN, (int) V32BF_FTYPE_V32BF_V32BF_INT_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_minmaxpv4df_mask, "__builtin_ia32_minmaxpd256_mask", IX86_BUILTIN_MINMAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_minmaxpv16hf_mask, "__builtin_ia32_minmaxph256_mask", IX86_BUILTIN_MINMAXPH256_MASK, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_INT_V16HF_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_minmaxpv8sf_mask, "__builtin_ia32_minmaxps256_mask", IX86_BUILTIN_MINMAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_minmaxpv2df_mask, "__builtin_ia32_minmaxpd128_mask", IX86_BUILTIN_MINMAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_minmaxpv8hf_mask, "__builtin_ia32_minmaxph128_mask", IX86_BUILTIN_MINMAXPH128_MASK, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_INT_V8HF_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_minmaxpv4sf_mask, "__builtin_ia32_minmaxps128_mask", IX86_BUILTIN_MINMAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_UQI)
 
 /* Builtins with rounding support.  */
 BDESC_END (ARGS, ROUND_ARGS)
@@ -3660,37 +3660,37 @@ BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fmulcsh_v8hf_round, "
 BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512fp16_fmulcsh_v8hf_mask_round, "__builtin_ia32_vfmulcsh_mask_round", IX86_BUILTIN_VFMULCSH_MASK_ROUND, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_V8HF_UQI_INT)
 
 /* AVX10.2.  */
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvt2ps2phx_v32hf_mask_round, "__builtin_ia32_vcvt2ps2phx512_mask_round", IX86_BUILTIN_VCVT2PS2PHX_V32HF_MASK_ROUND, UNKNOWN, (int) V32HF_FTYPE_V16SF_V16SF_V32HF_USI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvtph2ibsv32hf_mask_round, "__builtin_ia32_cvtph2ibs512_mask_round", IX86_BUILTIN_CVTPH2IBS512_MASK_ROUND, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvtph2iubsv32hf_mask_round, "__builtin_ia32_cvtph2iubs512_mask_round", IX86_BUILTIN_CVTPH2IUBS512_MASK_ROUND, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvtps2ibsv16sf_mask_round, "__builtin_ia32_cvtps2ibs512_mask_round", IX86_BUILTIN_CVTPS2IBS512_MASK_ROUND, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvtps2iubsv16sf_mask_round, "__builtin_ia32_cvtps2iubs512_mask_round", IX86_BUILTIN_CVTPS2IUBS512_MASK_ROUND, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvttph2ibsv32hf_mask_round, "__builtin_ia32_cvttph2ibs512_mask_round", IX86_BUILTIN_CVTTPH2IBS512_MASK_ROUND, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvttph2iubsv32hf_mask_round, "__builtin_ia32_cvttph2iubs512_mask_round", IX86_BUILTIN_CVTTPH2IUBS512_MASK_ROUND, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvttps2ibsv16sf_mask_round, "__builtin_ia32_cvttps2ibs512_mask_round", IX86_BUILTIN_CVTTPS2IBS512_MASK_ROUND, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvttps2iubsv16sf_mask_round, "__builtin_ia32_cvttps2iubs512_mask_round", IX86_BUILTIN_CVTTPS2IUBS512_MASK_ROUND, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vcvttpd2dqsv8df_mask_round, "__builtin_ia32_cvttpd2dqs512_mask_round", IX86_BUILTIN_VCVTTPD2DQS512_MASK_ROUND, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vcvttpd2qqsv8df_mask_round, "__builtin_ia32_cvttpd2qqs512_mask_round", IX86_BUILTIN_VCVTTPD2QQS512_MASK_ROUND, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vcvttpd2udqsv8df_mask_round, "__builtin_ia32_cvttpd2udqs512_mask_round", IX86_BUILTIN_VCVTTPD2UDQS512_MASK_ROUND, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vcvttpd2uqqsv8df_mask_round, "__builtin_ia32_cvttpd2uqqs512_mask_round", IX86_BUILTIN_VCVTTPD2UQQS512_MASK_ROUND, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vcvttps2dqsv16sf_mask_round, "__builtin_ia32_cvttps2dqs512_mask_round", IX86_BUILTIN_VCVTTPS2DQS512_MASK_ROUND, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vcvttps2qqsv8di_mask_round, "__builtin_ia32_cvttps2qqs512_mask_round", IX86_BUILTIN_VCVTTPS2QQS512_MASK_ROUND, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vcvttps2udqsv16sf_mask_round, "__builtin_ia32_cvttps2udqs512_mask_round", IX86_BUILTIN_VCVTTPS2UDQS512_MASK_ROUND, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_vcvttps2uqqsv8di_mask_round, "__builtin_ia32_cvttps2uqqs512_mask_round", IX86_BUILTIN_VCVTTPS2UQQS512_MASK_ROUND, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttsd2sissi_round, "__builtin_ia32_cvttsd2sis32_round", IX86_BUILTIN_VCVTTSD2SIS32_ROUND, UNKNOWN, (int) INT_FTYPE_V2DF_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttsd2sisdi_round, "__builtin_ia32_cvttsd2sis64_round", IX86_BUILTIN_VCVTTSD2SIS64_ROUND, UNKNOWN, (int) INT64_FTYPE_V2DF_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttsd2usissi_round, "__builtin_ia32_cvttsd2usis32_round", IX86_BUILTIN_VCVTTSD2USIS32_ROUND, UNKNOWN, (int) INT_FTYPE_V2DF_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttsd2usisdi_round, "__builtin_ia32_cvttsd2usis64_round", IX86_BUILTIN_VCVTTSD2USIS64_ROUND, UNKNOWN, (int) INT64_FTYPE_V2DF_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttss2sissi_round, "__builtin_ia32_cvttss2sis32_round", IX86_BUILTIN_VCVTTSS2SIS32_ROUND, UNKNOWN, (int) INT_FTYPE_V4SF_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttss2sisdi_round, "__builtin_ia32_cvttss2sis64_round", IX86_BUILTIN_VCVTTSS2SIS64_ROUND, UNKNOWN, (int) INT64_FTYPE_V4SF_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttss2usissi_round, "__builtin_ia32_cvttss2usis32_round", IX86_BUILTIN_VCVTTSS2USIS32_ROUND, UNKNOWN, (int) INT_FTYPE_V4SF_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_vcvttss2usisdi_round, "__builtin_ia32_cvttss2usis64_round", IX86_BUILTIN_VCVTTSS2USIS64_ROUND, UNKNOWN, (int) INT64_FTYPE_V4SF_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_minmaxpv8df_mask_round, "__builtin_ia32_minmaxpd512_mask_round", IX86_BUILTIN_MINMAXPD512_MASK_ROUND, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_UQI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_minmaxpv32hf_mask_round, "__builtin_ia32_minmaxph512_mask_round", IX86_BUILTIN_MINMAXPH512_MASK_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_INT_V32HF_USI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_minmaxpv16sf_mask_round, "__builtin_ia32_minmaxps512_mask_round", IX86_BUILTIN_MINMAXPS512_MASK_ROUND, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_UHI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_minmaxsv2df_mask_round, "__builtin_ia32_minmaxsd_mask_round", IX86_BUILTIN_MINMAXSD_MASK_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_UQI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_minmaxsv8hf_mask_round, "__builtin_ia32_minmaxsh_mask_round", IX86_BUILTIN_MINMAXSH_MASK_ROUND, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_INT_V8HF_UQI_INT)
-BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx10_2_minmaxsv4sf_mask_round, "__builtin_ia32_minmaxss_mask_round", IX86_BUILTIN_MINMAXSS_MASK_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvt2ps2phx_v32hf_mask_round, "__builtin_ia32_vcvt2ps2phx512_mask_round", IX86_BUILTIN_VCVT2PS2PHX_V32HF_MASK_ROUND, UNKNOWN, (int) V32HF_FTYPE_V16SF_V16SF_V32HF_USI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtph2ibsv32hf_mask_round, "__builtin_ia32_cvtph2ibs512_mask_round", IX86_BUILTIN_CVTPH2IBS512_MASK_ROUND, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtph2iubsv32hf_mask_round, "__builtin_ia32_cvtph2iubs512_mask_round", IX86_BUILTIN_CVTPH2IUBS512_MASK_ROUND, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtps2ibsv16sf_mask_round, "__builtin_ia32_cvtps2ibs512_mask_round", IX86_BUILTIN_CVTPS2IBS512_MASK_ROUND, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvtps2iubsv16sf_mask_round, "__builtin_ia32_cvtps2iubs512_mask_round", IX86_BUILTIN_CVTPS2IUBS512_MASK_ROUND, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttph2ibsv32hf_mask_round, "__builtin_ia32_cvttph2ibs512_mask_round", IX86_BUILTIN_CVTTPH2IBS512_MASK_ROUND, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttph2iubsv32hf_mask_round, "__builtin_ia32_cvttph2iubs512_mask_round", IX86_BUILTIN_CVTTPH2IUBS512_MASK_ROUND, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttps2ibsv16sf_mask_round, "__builtin_ia32_cvttps2ibs512_mask_round", IX86_BUILTIN_CVTTPS2IBS512_MASK_ROUND, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_cvttps2iubsv16sf_mask_round, "__builtin_ia32_cvttps2iubs512_mask_round", IX86_BUILTIN_CVTTPS2IUBS512_MASK_ROUND, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_UHI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttpd2dqsv8df_mask_round, "__builtin_ia32_cvttpd2dqs512_mask_round", IX86_BUILTIN_VCVTTPD2DQS512_MASK_ROUND, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttpd2qqsv8df_mask_round, "__builtin_ia32_cvttpd2qqs512_mask_round", IX86_BUILTIN_VCVTTPD2QQS512_MASK_ROUND, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttpd2udqsv8df_mask_round, "__builtin_ia32_cvttpd2udqs512_mask_round", IX86_BUILTIN_VCVTTPD2UDQS512_MASK_ROUND, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttpd2uqqsv8df_mask_round, "__builtin_ia32_cvttpd2uqqs512_mask_round", IX86_BUILTIN_VCVTTPD2UQQS512_MASK_ROUND, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttps2dqsv16sf_mask_round, "__builtin_ia32_cvttps2dqs512_mask_round", IX86_BUILTIN_VCVTTPS2DQS512_MASK_ROUND, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttps2qqsv8di_mask_round, "__builtin_ia32_cvttps2qqs512_mask_round", IX86_BUILTIN_VCVTTPS2QQS512_MASK_ROUND, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttps2udqsv16sf_mask_round, "__builtin_ia32_cvttps2udqs512_mask_round", IX86_BUILTIN_VCVTTPS2UDQS512_MASK_ROUND, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttps2uqqsv8di_mask_round, "__builtin_ia32_cvttps2uqqs512_mask_round", IX86_BUILTIN_VCVTTPS2UQQS512_MASK_ROUND, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttsd2sissi_round, "__builtin_ia32_cvttsd2sis32_round", IX86_BUILTIN_VCVTTSD2SIS32_ROUND, UNKNOWN, (int) INT_FTYPE_V2DF_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttsd2sisdi_round, "__builtin_ia32_cvttsd2sis64_round", IX86_BUILTIN_VCVTTSD2SIS64_ROUND, UNKNOWN, (int) INT64_FTYPE_V2DF_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttsd2usissi_round, "__builtin_ia32_cvttsd2usis32_round", IX86_BUILTIN_VCVTTSD2USIS32_ROUND, UNKNOWN, (int) INT_FTYPE_V2DF_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttsd2usisdi_round, "__builtin_ia32_cvttsd2usis64_round", IX86_BUILTIN_VCVTTSD2USIS64_ROUND, UNKNOWN, (int) INT64_FTYPE_V2DF_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttss2sissi_round, "__builtin_ia32_cvttss2sis32_round", IX86_BUILTIN_VCVTTSS2SIS32_ROUND, UNKNOWN, (int) INT_FTYPE_V4SF_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttss2sisdi_round, "__builtin_ia32_cvttss2sis64_round", IX86_BUILTIN_VCVTTSS2SIS64_ROUND, UNKNOWN, (int) INT64_FTYPE_V4SF_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttss2usissi_round, "__builtin_ia32_cvttss2usis32_round", IX86_BUILTIN_VCVTTSS2USIS32_ROUND, UNKNOWN, (int) INT_FTYPE_V4SF_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_vcvttss2usisdi_round, "__builtin_ia32_cvttss2usis64_round", IX86_BUILTIN_VCVTTSS2USIS64_ROUND, UNKNOWN, (int) INT64_FTYPE_V4SF_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_minmaxpv8df_mask_round, "__builtin_ia32_minmaxpd512_mask_round", IX86_BUILTIN_MINMAXPD512_MASK_ROUND, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_minmaxpv32hf_mask_round, "__builtin_ia32_minmaxph512_mask_round", IX86_BUILTIN_MINMAXPH512_MASK_ROUND, UNKNOWN, (int) V32HF_FTYPE_V32HF_V32HF_INT_V32HF_USI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_minmaxpv16sf_mask_round, "__builtin_ia32_minmaxps512_mask_round", IX86_BUILTIN_MINMAXPS512_MASK_ROUND, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_UHI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_minmaxsv2df_mask_round, "__builtin_ia32_minmaxsd_mask_round", IX86_BUILTIN_MINMAXSD_MASK_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_minmaxsv8hf_mask_round, "__builtin_ia32_minmaxsh_mask_round", IX86_BUILTIN_MINMAXSH_MASK_ROUND, UNKNOWN, (int) V8HF_FTYPE_V8HF_V8HF_INT_V8HF_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2, CODE_FOR_avx10_2_minmaxsv4sf_mask_round, "__builtin_ia32_minmaxss_mask_round", IX86_BUILTIN_MINMAXSS_MASK_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_UQI_INT)
 
 BDESC_END (ROUND_ARGS, MULTI_ARG)
 

diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc
index 7e310c36b56ae34218a46afb82a585c4ed40d1c7..e6daba94a6fb5860becce7dff7728c79326aa50b 100644 (file)
--- a/gcc/config/i386/i386-c.cc
+++ b/gcc/config/i386/i386-c.cc
@@ -744,10 +744,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
     def_or_undef (parse_in, "__APX_F__");
   if (ix86_apx_inline_asm_use_gpr32)
     def_or_undef (parse_in, "__APX_INLINE_ASM_USE_GPR32__");
-  if (isa_flag2 & OPTION_MASK_ISA2_AVX10_2_256)
-    def_or_undef (parse_in, "__AVX10_2_256__");
-  if (isa_flag2 & OPTION_MASK_ISA2_AVX10_2_512)
-    def_or_undef (parse_in, "__AVX10_2_512__");
+  if (isa_flag2 & OPTION_MASK_ISA2_AVX10_2)
+    def_or_undef (parse_in, "__AVX10_2__");
   if (isa_flag2 & OPTION_MASK_ISA2_AMX_AVX512)
     def_or_undef (parse_in, "__AMX_AVX512__");
   if (isa_flag2 & OPTION_MASK_ISA2_AMX_TF32)

diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index bceffa05c966bffe4b10bc861a286124507c8435..cdfd94d3c73d7f0414c84da10a2d3d12a8789453 100644 (file)
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -2531,7 +2531,7 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label)
       return;
 
     case E_BFmode:
-      gcc_assert (TARGET_AVX10_2_256 && !flag_trapping_math);
+      gcc_assert (TARGET_AVX10_2 && !flag_trapping_math);
       goto simple;
 
     case E_DImode:
@@ -2802,7 +2802,7 @@ ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
   machine_mode op_mode = GET_MODE (op0);
   bool is_sse = SSE_FLOAT_MODE_SSEMATH_OR_HFBF_P (op_mode);
 
-  if (op_mode == BFmode && (!TARGET_AVX10_2_256 || flag_trapping_math))
+  if (op_mode == BFmode && (!TARGET_AVX10_2 || flag_trapping_math))
     {
       rtx op = gen_lowpart (HImode, op0);
       if (CONST_INT_P (op))
@@ -2924,7 +2924,7 @@ ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1)
       /* We only have vcomisbf16, No vcomubf16 nor vcomxbf16 */
       if (GET_MODE (op0) != E_BFmode)
        {
-         if (TARGET_AVX10_2_256 && (code == EQ || code == NE))
+         if (TARGET_AVX10_2 && (code == EQ || code == NE))
            tmp = gen_rtx_UNSPEC (CCFPmode, gen_rtvec (1, tmp), UNSPEC_OPTCOMX);
          if (unordered_compare)
            tmp = gen_rtx_UNSPEC (CCFPmode, gen_rtvec (1, tmp), UNSPEC_NOTRAP);
@@ -10779,7 +10779,7 @@ ix86_ssecom_setcc (const enum rtx_code comparison,
 
   /* NB: For ordered EQ or unordered NE, check ZF alone isn't sufficient
      with NAN operands.
-     Under TARGET_AVX10_2_256, VCOMX/VUCOMX are generated instead of
+     Under TARGET_AVX10_2, VCOMX/VUCOMX are generated instead of
      COMI/UCOMI.  VCOMX/VUCOMX will not set ZF for NAN operands.  */
   if (check_unordered)
     {
@@ -10852,12 +10852,12 @@ ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
     case GE:
       break;
     case EQ:
-      if (!TARGET_AVX10_2_256 || !comx_ok)
+      if (!TARGET_AVX10_2 || !comx_ok)
        check_unordered = true;
       mode = CCZmode;
       break;
     case NE:
-      if (!TARGET_AVX10_2_256 || !comx_ok)
+      if (!TARGET_AVX10_2 || !comx_ok)
        check_unordered = true;
       mode = CCZmode;
       const_val = const1_rtx;
@@ -10878,7 +10878,7 @@ ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
     op1 = copy_to_mode_reg (mode1, op1);
 
   if ((comparison == EQ || comparison == NE)
-      && TARGET_AVX10_2_256 && comx_ok)
+      && TARGET_AVX10_2 && comx_ok)
     {
       switch (icode)
        {
@@ -12474,7 +12474,7 @@ ix86_expand_sse_comi_round (const struct builtin_description *d,
     case ORDERED:
       if (!ordered)
        {
-         if (TARGET_AVX10_2_256 && comx_ok)
+         if (TARGET_AVX10_2 && comx_ok)
            {
              /* Unlike VCOMI{SH,SS,SD}, VCOMX{SH,SS,SD} will set SF
                 differently. So directly return true here.  */
@@ -12502,7 +12502,7 @@ ix86_expand_sse_comi_round (const struct builtin_description *d,
     case UNORDERED:
       if (ordered)
        {
-         if (TARGET_AVX10_2_256 && comx_ok)
+         if (TARGET_AVX10_2 && comx_ok)
            {
              /* Unlike VCOMI{SH,SS,SD}, VCOMX{SH,SS,SD} will set SF
                 differently. So directly return false here.  */
@@ -12549,20 +12549,20 @@ ix86_expand_sse_comi_round (const struct builtin_description *d,
       break;
       /* NB: COMI/UCOMI will set ZF with NAN operands.  Use CCZmode for
         _CMP_EQ_OQ/_CMP_EQ_OS.
-        Under TARGET_AVX10_2_256, VCOMX/VUCOMX are always generated instead
+        Under TARGET_AVX10_2, VCOMX/VUCOMX are always generated instead
         of COMI/UCOMI, VCOMX/VUCOMX will not set ZF with NAN.  */
     case EQ:
-      if (!TARGET_AVX10_2_256 || !comx_ok)
+      if (!TARGET_AVX10_2 || !comx_ok)
        check_unordered = true;
       mode = CCZmode;
       break;
     case NE:
       /* NB: COMI/UCOMI will set ZF with NAN operands.  Use CCZmode for
         _CMP_NEQ_UQ/_CMP_NEQ_US.
-        Under TARGET_AVX10_2_256, VCOMX/VUCOMX are always generated instead
+        Under TARGET_AVX10_2, VCOMX/VUCOMX are always generated instead
         of COMI/UCOMI, VCOMX/VUCOMX will not set ZF with NAN.  */
       gcc_assert (!ordered);
-      if (!TARGET_AVX10_2_256 || !comx_ok)
+      if (!TARGET_AVX10_2 || !comx_ok)
        check_unordered = true;
       mode = CCZmode;
       const_val = const1_rtx;
@@ -12585,7 +12585,7 @@ ix86_expand_sse_comi_round (const struct builtin_description *d,
     /* Generate comx instead of comi when EQ/NE to avoid NAN checks.
        Use orig_comp to exclude ORDERED/UNORDERED cases.  */
   if ((orig_comp == EQ || orig_comp == NE)
-      && TARGET_AVX10_2_256 && comx_ok)
+      && TARGET_AVX10_2 && comx_ok)
     {
       switch (icode)
        {
@@ -12606,7 +12606,7 @@ ix86_expand_sse_comi_round (const struct builtin_description *d,
 
   /* Generate comi instead of comx when UNEQ/LTGT to avoid NAN checks.  */
   if ((comparison == UNEQ || comparison == LTGT)
-       && TARGET_AVX10_2_256 && comx_ok)
+       && TARGET_AVX10_2 && comx_ok)
     {
       switch (icode)
        {
@@ -13582,9 +13582,9 @@ ix86_check_builtin_isa_match (unsigned int fcode,
   SHARE_BUILTIN (OPTION_MASK_ISA_AES, 0, OPTION_MASK_ISA_AVX512VL,
                 OPTION_MASK_ISA2_VAES);
   SHARE_BUILTIN (0, OPTION_MASK_ISA2_AVXVNNIINT8, 0,
-                OPTION_MASK_ISA2_AVX10_2_256);
+                OPTION_MASK_ISA2_AVX10_2);
   SHARE_BUILTIN (0, OPTION_MASK_ISA2_AVXVNNIINT16, 0,
-                OPTION_MASK_ISA2_AVX10_2_256);
+                OPTION_MASK_ISA2_AVX10_2);
   isa = tmp_isa;
   isa2 = tmp_isa2;
 

diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def
index 5d8db3616e7e408ee45196fc18c32de120381769..13cb49a75bb39ba9cd3e1a6aaf882e496cf954fc 100644 (file)
--- a/gcc/config/i386/i386-isa.def
+++ b/gcc/config/i386/i386-isa.def
@@ -121,8 +121,7 @@ DEF_PTA(USER_MSR)
 DEF_PTA(EVEX512)
 DEF_PTA(AVX10_1_256)
 DEF_PTA(AVX10_1_512)
-DEF_PTA(AVX10_2_256)
-DEF_PTA(AVX10_2_512)
+DEF_PTA(AVX10_2)
 DEF_PTA(AMX_AVX512)
 DEF_PTA(AMX_TF32)
 DEF_PTA(AMX_TRANSPOSE)

diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index fc4d2d2529edce2771575c9fb93b149e1abd688a..a48a939db3f762deec1141a574c85f77fd694283 100644 (file)
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -263,8 +263,7 @@ static struct ix86_target_opts isa2_opts[] =
   { "-musermsr",       OPTION_MASK_ISA2_USER_MSR },
   { "-mavx10.1-256",   OPTION_MASK_ISA2_AVX10_1_256 },
   { "-mavx10.1-512",   OPTION_MASK_ISA2_AVX10_1_512 },
-  { "-mavx10.2-256",   OPTION_MASK_ISA2_AVX10_2_256 },
-  { "-mavx10.2-512",   OPTION_MASK_ISA2_AVX10_2_512 },
+  { "-mavx10.2",       OPTION_MASK_ISA2_AVX10_2 },
   { "-mamx-avx512",    OPTION_MASK_ISA2_AMX_AVX512 },
   { "-mamx-tf32",      OPTION_MASK_ISA2_AMX_TF32 },
   { "-mamx-transpose", OPTION_MASK_ISA2_AMX_TRANSPOSE },
@@ -1136,9 +1135,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],
     IX86_ATTR_ISA ("usermsr", OPT_musermsr),
     IX86_ATTR_ISA ("avx10.1-256", OPT_mavx10_1_256),
     IX86_ATTR_ISA ("avx10.1-512", OPT_mavx10_1_512),
-    IX86_ATTR_ISA ("avx10.2-256", OPT_mavx10_2_256),
     IX86_ATTR_ISA ("avx10.2", OPT_mavx10_2),
-    IX86_ATTR_ISA ("avx10.2-512", OPT_mavx10_2),
     IX86_ATTR_ISA ("amx-avx512", OPT_mamx_avx512),
     IX86_ATTR_ISA ("amx-tf32", OPT_mamx_tf32),
     IX86_ATTR_ISA ("amx-transpose", OPT_mamx_transpose),

diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index be5e27fc391fd419787eb15df9b090d8b16265ae..18127bcada81669f150e90c1bc80f9d9993a2a49 100644 (file)
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -16668,7 +16668,7 @@ ix86_fp_compare_code_to_integer (enum rtx_code code)
       return NE;
     case EQ:
     case NE:
-      if (TARGET_AVX10_2_256)
+      if (TARGET_AVX10_2)
        return code;
       /* FALLTHRU.  */
     default:
@@ -25055,7 +25055,7 @@ ix86_get_mask_mode (machine_mode data_mode)
         to kmask for _Float16.  */
       || (TARGET_AVX512VL && TARGET_AVX512FP16
          && GET_MODE_INNER (data_mode) == E_HFmode)
-      || (TARGET_AVX10_2_256 && GET_MODE_INNER (data_mode) == E_BFmode))
+      || (TARGET_AVX10_2 && GET_MODE_INNER (data_mode) == E_BFmode))
     {
       if (elem_size == 4
          || elem_size == 8

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index ce29c272bc0bd5125a1a90b05704e3a27e4a1009..c797ac1c5d037fdcdc1f4e5a8b57523644cb15eb 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1176,7 +1176,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
 #define SSE_FLOAT_MODE_SSEMATH_OR_HFBF_P(MODE)                          \
   ((SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH)                         \
    || (TARGET_AVX512FP16 && (MODE) == HFmode)                           \
-   || (TARGET_AVX10_2_256 && (MODE) == BFmode))
+   || (TARGET_AVX10_2 && (MODE) == BFmode))
 
 #define FMA4_VEC_FLOAT_MODE_P(MODE) \
   (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
@@ -2451,7 +2451,7 @@ constexpr wide_int_bitmask PTA_DIAMONDRAPIDS = PTA_SKYLAKE | PTA_PKU | PTA_SHA
   | PTA_AMX_TILE | PTA_AMX_INT8 | PTA_AMX_BF16 | PTA_UINTR | PTA_AVXVNNI
   | PTA_AMX_FP16 | PTA_PREFETCHI | PTA_AMX_COMPLEX | PTA_AVX10_1_512
   | PTA_AVXIFMA | PTA_AVXNECONVERT | PTA_AVXVNNIINT16 | PTA_AVXVNNIINT8
-  | PTA_CMPCCXADD | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_AVX10_2_512
+  | PTA_CMPCCXADD | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_AVX10_2
   | PTA_APX_F | PTA_AMX_AVX512 | PTA_AMX_FP8 | PTA_AMX_TF32 | PTA_AMX_TRANSPOSE
   | PTA_MOVRS | PTA_AMX_MOVRS | PTA_USER_MSR;
 

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 8c7beafd758e87f3928e4ab59958eb06d821be50..2b3cffc1f35093be35f42a9b7618b58a1cf30830 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -984,7 +984,7 @@
           (symbol_ref "TARGET_APX_NDD && Pmode == DImode")
         (eq_attr "isa" "vaes_avx512vl")
           (symbol_ref "TARGET_VAES && TARGET_AVX512VL")
-        (eq_attr "isa" "avx10_2") (symbol_ref "TARGET_AVX10_2_256")
+        (eq_attr "isa" "avx10_2") (symbol_ref "TARGET_AVX10_2")
 
         (eq_attr "mmx_isa" "native")
           (symbol_ref "!TARGET_MMX_WITH_SSE")
@@ -1819,7 +1819,7 @@
              (pc)))]
   "TARGET_80387 || (SSE_FLOAT_MODE_P (SFmode) && TARGET_SSE_MATH)"
 {
-  if (TARGET_AVX10_2_256 && !flag_trapping_math)
+  if (TARGET_AVX10_2 && !flag_trapping_math)
     ix86_expand_branch (GET_CODE (operands[0]),
                        operands[1], operands[2], operands[3]);
   else
@@ -1861,7 +1861,7 @@
   "TARGET_80387 || (SSE_FLOAT_MODE_P (SFmode) && TARGET_SSE_MATH)"
 {
   rtx op2 = operands[2], op3 = operands[3];
-  if (!TARGET_AVX10_2_256 || flag_trapping_math)
+  if (!TARGET_AVX10_2 || flag_trapping_math)
     {
       op2 = ix86_expand_fast_convert_bf_to_sf (operands[2]);
       op3 = ix86_expand_fast_convert_bf_to_sf (operands[3]);
@@ -2042,7 +2042,7 @@
            (match_operand:MODEF 0 "register_operand" "v")
            (match_operand:MODEF 1 "nonimmediate_operand" "vm"))]
          UNSPEC_OPTCOMX))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "%v<unord>comx<MODEF:ssemodesuffix>\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecomi")
    (set_attr "prefix" "evex")
@@ -2055,7 +2055,7 @@
            (match_operand:HF 0 "register_operand" "v")
            (match_operand:HF 1 "nonimmediate_operand" "vm"))]
          UNSPEC_OPTCOMX))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "v<unord>comxsh\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecomi")
    (set_attr "prefix" "evex")
@@ -2114,7 +2114,7 @@
        (compare:CCFP
          (match_operand:BF 0 "register_operand" "v")
          (match_operand:BF 1 "nonimmediate_operand" "vm")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vcomisbf16\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecomi")
    (set_attr "prefix" "evex")

diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 9dc607367ece0323eaae00992e4e9df2cabd476b..ff864b68720257fdffb56dfdf3848d1aa433ecd9 100644 (file)
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1366,32 +1366,22 @@ Support USER_MSR built-in functions and code generation.
 mavx10.1-256
 Target Mask(ISA2_AVX10_1_256) Var(ix86_isa_flags2) Save
 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
-and AVX10.1 built-in functions and code generation.
+and AVX10.1-256 built-in functions and code generation.
 
 mavx10.1-512
 Target Mask(ISA2_AVX10_1_512) Var(ix86_isa_flags2) Save
 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
 and AVX10.1-512 built-in functions and code generation.
 
-mavx10.2-256
-Target RejectNegative Mask(ISA2_AVX10_2_256) Var(ix86_isa_flags2) Save
-Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
-AVX10.1 and AVX10.2 built-in functions and code generation.
-
 mavx10.2
-Target Mask(ISA2_AVX10_2_512) Var(ix86_isa_flags2) Save
-Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
-AVX10.1-512 and AVX10.2-512 built-in functions and code generation.
-
-mavx10.2-512
-Target RejectNegative Alias(mavx10.2)
+Target Mask(ISA2_AVX10_2) Var(ix86_isa_flags2) Save
 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
-AVX10.1-512 and AVX10.2-512 built-in functions and code generation.
+AVX10.1-512 and AVX10.2 built-in functions and code generation.
 
 mamx-avx512
 Target Mask(ISA2_AMX_AVX512) Var(ix86_isa_flags2) Save
 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX10.1-512,
-AVX10.2-512 and AMX-AVX512 built-in functions and code generation.
+AVX10.2 and AMX-AVX512 built-in functions and code generation.
 
 mamx-tf32
 Target Mask(ISA2_AMX_TF32) Var(ix86_isa_flags2) Save

diff --git a/gcc/config/i386/i386.opt.urls b/gcc/config/i386/i386.opt.urls
index ee6806169df6668330f23f0844254bd07ef4397d..abfb97302b85654fb87c868d4ef38d68ba9374b9 100644 (file)
--- a/gcc/config/i386/i386.opt.urls
+++ b/gcc/config/i386/i386.opt.urls
@@ -602,15 +602,9 @@ UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1-256)
 mavx10.1-512
 UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1-512)
 
-mavx10.2-256
-UrlSuffix(gcc/x86-Options.html#index-mavx10_002e2-256)
-
 mavx10.2
 UrlSuffix(gcc/x86-Options.html#index-mavx10_002e2)
 
-mavx10.2-512
-UrlSuffix(gcc/x86-Options.html#index-mavx10_002e2-512)
-
 mamx-avx512
 UrlSuffix(gcc/x86-Options.html#index-mamx-avx512)
 

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index e51899939717cc56bf43d246eef00598604e9f83..79202323e534b6afd6f3de392874034e2209658e 100644 (file)
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -2117,7 +2117,7 @@
     (plusminusmultdiv:VBF_32_64
       (match_operand:VBF_32_64 1 "nonimmediate_operand")
       (match_operand:VBF_32_64 2 "nonimmediate_operand")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
 {
   rtx op0 = gen_reg_rtx (V8BFmode);
   rtx op1 = lowpart_subreg (V8BFmode,
@@ -2176,7 +2176,7 @@
     (smaxmin:VBF_32_64
       (match_operand:VBF_32_64 1 "nonimmediate_operand")
       (match_operand:VBF_32_64 2 "nonimmediate_operand")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
 {
   rtx op0 = gen_reg_rtx (V8BFmode);
   rtx op1 = lowpart_subreg (V8BFmode,
@@ -2208,7 +2208,7 @@
 (define_expand "sqrt<mode>2"
   [(set (match_operand:VBF_32_64 0 "register_operand")
        (sqrt:VBF_32_64 (match_operand:VBF_32_64 1 "vector_operand")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
 {
   rtx op0 = gen_reg_rtx (V8BFmode);
   rtx op1 = lowpart_subreg (V8BFmode,
@@ -2369,7 +2369,7 @@
        (match_operator:QI 1 ""
          [(match_operand:VBF_32_64 2 "register_operand")
           (match_operand:VBF_32_64 3 "nonimmediate_operand")]))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
 {
   rtx op2 = lowpart_subreg (V8BFmode,
                             force_reg (<MODE>mode, operands[2]), <MODE>mode);
@@ -2788,7 +2788,7 @@
          (match_operand:VBF_32_64 1 "nonimmediate_operand")
          (match_operand:VBF_32_64 2 "nonimmediate_operand")
          (match_operand:VBF_32_64 3 "nonimmediate_operand")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
 {
   rtx op0 = gen_reg_rtx (V8BFmode);
   rtx op1 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[1]), <MODE>mode);
@@ -2808,7 +2808,7 @@
          (match_operand:VBF_32_64   2 "nonimmediate_operand")
          (neg:VBF_32_64
            (match_operand:VBF_32_64 3 "nonimmediate_operand"))))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
 {
   rtx op0 = gen_reg_rtx (V8BFmode);
   rtx op1 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[1]), <MODE>mode);
@@ -2828,7 +2828,7 @@
            (match_operand:VBF_32_64 1 "nonimmediate_operand"))
          (match_operand:VBF_32_64   2 "nonimmediate_operand")
          (match_operand:VBF_32_64   3 "nonimmediate_operand")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
 {
   rtx op0 = gen_reg_rtx (V8BFmode);
   rtx op1 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[1]), <MODE>mode);
@@ -2849,7 +2849,7 @@
          (match_operand:VBF_32_64   2 "nonimmediate_operand")
          (neg:VBF_32_64
            (match_operand:VBF_32_64 3 "nonimmediate_operand"))))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
 {
   rtx op0 = gen_reg_rtx (V8BFmode);
   rtx op1 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[1]), <MODE>mode);

diff --git a/gcc/config/i386/movrsintrin.h b/gcc/config/i386/movrsintrin.h
index b29d64371fbf0ad6a0284d93519d3cc303694159..9127442d2cae49a8e3cc5aee5f95780d1c1b179b 100644 (file)
--- a/gcc/config/i386/movrsintrin.h
+++ b/gcc/config/i386/movrsintrin.h
@@ -79,7 +79,7 @@ _movrs_i64 (void const * __P)
 
 #ifdef __x86_64__
 
-#if !defined (__AVX10_2_256__) || !defined (__MOVRS__)
+#if !defined (__AVX10_2__) || !defined (__MOVRS__)
 #pragma GCC push_options
 #pragma GCC target("avx10.2,movrs")
 #define __DISABLE_MOVRS_AVX10_2__
@@ -317,17 +317,6 @@ _mm_maskz_loadrs_epi16 (__mmask8 __U, void const *__A)
                                                   (__mmask8) __U);
 }
 
-#ifdef __DISABLE_MOVRS_AVX10_2__
-#undef __DISABLE_MOVRS_AVX10_2__
-#pragma GCC pop_options
-#endif /* __DISABLE_MOVRS_AVX10_2__ */
-
-#if !defined (__AVX10_2_512__) || !defined (__MOVRS__)
-#pragma GCC push_options
-#pragma GCC target("avx10.2-512,movrs")
-#define __DISABLE_MOVRS_AVX10_2_512__
-#endif /* __MOVRS_AVX10_2_512__ */
-
 extern __inline __m512i
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm512_loadrs_epi8 (void const *__A)
@@ -443,10 +432,10 @@ _mm512_maskz_loadrs_epi16 (__mmask32 __U, void const *__A)
                                                   (__mmask32) __U);
 }
 
-#ifdef __DISABLE_MOVRS_AVX10_2_512__
-#undef __DISABLE_MOVRS_AVX10_2_512__
+#ifdef __DISABLE_MOVRS_AVX10_2__
+#undef __DISABLE_MOVRS_AVX10_2__
 #pragma GCC pop_options
-#endif /* __DISABLE_MOVRS_AVX10_2_512__ */
+#endif /* __DISABLE_MOVRS_AVX10_2__ */
 
 #endif /* __x86_64__ */
 

diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 8631588f78e0c11df54814426465dd3b39fe4f57..3d3848c0a2262bc2f401d20f32093a6132606243 100644 (file)
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -1629,7 +1629,7 @@
 ;; Return true if this comparison only requires testing one flag bit.
 ;; VCOMX/VUCOMX set ZF, SF, OF, differently from COMI/UCOMI.
 (define_predicate "ix86_trivial_fp_comparison_operator"
-  (if_then_else (match_test "TARGET_AVX10_2_256")
+  (if_then_else (match_test "TARGET_AVX10_2")
                (match_code "gt,ge,unlt,unle,eq,uneq,ne,ltgt,ordered,unordered")
                (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered")))
 

diff --git a/gcc/config/i386/sm4intrin.h b/gcc/config/i386/sm4intrin.h
index 29d1d4c0ab3d68f990b346eeb959a4d29a632706..af7a1c38984191e90d6d7c7d8a60a95575606e1e 100644 (file)
--- a/gcc/config/i386/sm4intrin.h
+++ b/gcc/config/i386/sm4intrin.h
@@ -67,9 +67,9 @@ _mm256_sm4rnds4_epi32 (__m256i __A, __m256i __B)
 #pragma GCC pop_options
 #endif /* __DISABLE_SM4__ */
 
-#if !defined (__SM4__) || !defined (__AVX10_2_512__)
+#if !defined (__SM4__) || !defined (__AVX10_2__)
 #pragma GCC push_options
-#pragma GCC target("sm4,avx10.2-512")
+#pragma GCC target("sm4,avx10.2")
 #define __DISABLE_SM4_512__
 #endif /* __SM4_512__ */
 

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 0ded0d5f9e5edef5e678702e186b81185be7af0d..ee2a482fb509b1c6a307186e288078e07e2995fa 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -382,8 +382,8 @@
    (V2DF "TARGET_AVX512DQ && TARGET_AVX512VL")])
 
 (define_mode_iterator VF1_VF2_AVX10_2
-  [(V16SF "TARGET_AVX10_2_512") V8SF V4SF
-   (V8DF "TARGET_AVX10_2_512") V4DF V2DF])
+  [(V16SF "TARGET_AVX10_2") V8SF V4SF
+   (V8DF "TARGET_AVX10_2") V4DF V2DF])
 
 (define_mode_iterator VFH
   [(V32HF "TARGET_AVX512FP16 && TARGET_EVEX512")
@@ -401,9 +401,9 @@
    (V8SF "TARGET_AVX") V4SF
    (V8DF "TARGET_AVX512F && TARGET_EVEX512")
    (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")
-   (V32BF "TARGET_AVX10_2_512")
-   (V16BF "TARGET_AVX10_2_256")
-   (V8BF "TARGET_AVX10_2_256")
+   (V32BF "TARGET_AVX10_2")
+   (V16BF "TARGET_AVX10_2")
+   (V8BF "TARGET_AVX10_2")
   ])
 
 ;; 128-, 256- and 512-bit float vector modes for bitwise operations
@@ -447,13 +447,13 @@
   [(V8DF "TARGET_AVX512F && TARGET_EVEX512") (V4DF "TARGET_AVX") V2DF])
 
 (define_mode_iterator VF2_AVX10_2
-  [(V8DF "TARGET_AVX10_2_512") V4DF V2DF])
+  [(V8DF "TARGET_AVX10_2") V4DF V2DF])
 
 ;; All DFmode & HFmode & BFmode vector float modes
 (define_mode_iterator VF2HB
-  [(V32BF "TARGET_AVX10_2_512")
-   (V16BF "TARGET_AVX10_2_256")
-   (V8BF "TARGET_AVX10_2_256")
+  [(V32BF "TARGET_AVX10_2")
+   (V16BF "TARGET_AVX10_2")
+   (V8BF "TARGET_AVX10_2")
    (V32HF "TARGET_AVX512FP16 && TARGET_EVEX512")
    (V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL")
    (V8HF "TARGET_AVX512FP16 && TARGET_AVX512VL")
@@ -511,10 +511,10 @@
    (V8DI "TARGET_EVEX512") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")])
 
 (define_mode_iterator VI1248_AVX10_2
-  [(V64QI "TARGET_AVX10_2_512") V32QI V16QI
-   (V32HI "TARGET_AVX10_2_512") V16HI V8HI
-   (V16SI "TARGET_AVX10_2_512") V8SI V4SI
-   (V8DI "TARGET_AVX10_2_512") V4DI V2DI])
+  [(V64QI "TARGET_AVX10_2") V32QI V16QI
+   (V32HI "TARGET_AVX10_2") V16HI V8HI
+   (V16SI "TARGET_AVX10_2") V8SI V4SI
+   (V8DI "TARGET_AVX10_2") V4DI V2DI])
 
 (define_mode_iterator VF_AVX512VL
   [(V16SF "TARGET_EVEX512") (V8SF "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL")
@@ -528,9 +528,9 @@
    (V8DF "TARGET_EVEX512") (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")])
 
 (define_mode_iterator VFH_AVX10_2
-  [(V32HF "TARGET_AVX10_2_512") V16HF V8HF
-   (V16SF "TARGET_AVX10_2_512") V8SF V4SF
-   (V8DF "TARGET_AVX10_2_512") V4DF V2DF])
+  [(V32HF "TARGET_AVX10_2") V16HF V8HF
+   (V16SF "TARGET_AVX10_2") V8SF V4SF
+   (V8DF "TARGET_AVX10_2") V4DF V2DF])
 
 (define_mode_iterator VF2_AVX512VL
   [(V8DF "TARGET_EVEX512") (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")])
@@ -542,7 +542,7 @@
   [(V16SF "TARGET_AVX512BW && TARGET_EVEX512") (V8SF "TARGET_AVX2") V4SF])
 
 (define_mode_iterator VF1_AVX10_2
-  [(V16SF "TARGET_AVX10_2_512") V8SF V4SF])
+  [(V16SF "TARGET_AVX10_2") V8SF V4SF])
 
 (define_mode_iterator VHFBF
   [(V32HF "TARGET_EVEX512") V16HF V8HF
@@ -558,10 +558,10 @@
    (V32BF "TARGET_EVEX512") (V16BF "TARGET_AVX512VL") (V8BF "TARGET_AVX512VL")])
 
 (define_mode_iterator VHF_AVX10_2
-  [(V32HF "TARGET_AVX10_2_512") V16HF V8HF])
+  [(V32HF "TARGET_AVX10_2") V16HF V8HF])
 
 (define_mode_iterator VBF_AVX10_2
-  [(V32BF "TARGET_AVX10_2_512") V16BF V8BF])
+  [(V32BF "TARGET_AVX10_2") V16BF V8BF])
 
 ;; All vector integer modes
 (define_mode_iterator VI
@@ -614,7 +614,7 @@
   [(V8DI "TARGET_AVX512F && TARGET_EVEX512") (V4DI "TARGET_AVX") V2DI])
 
 (define_mode_iterator VI8_AVX10_2
-  [(V8DI "TARGET_AVX10_2_512") V4DI V2DI])
+  [(V8DI "TARGET_AVX10_2") V4DI V2DI])
 
 (define_mode_iterator VI8_FVL
   [(V8DI "TARGET_AVX512F && TARGET_EVEX512") V4DI (V2DI "TARGET_AVX512VL")])
@@ -659,7 +659,7 @@
    (V16HI "TARGET_AVX2") V8HI])
 
 (define_mode_iterator VI2_AVX10_2
-  [(V32HI "TARGET_AVX10_2_512") V16HI V8HI])
+  [(V32HI "TARGET_AVX10_2") V16HI V8HI])
 
 (define_mode_iterator VI4_AVX
   [(V8SI "TARGET_AVX") V4SI])
@@ -674,7 +674,7 @@
   [(V16SI "TARGET_EVEX512") (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")])
 
 (define_mode_iterator VI4_AVX10_2
-  [(V16SI "TARGET_AVX10_2_512") V8SI V4SI])
+  [(V16SI "TARGET_AVX10_2") V8SI V4SI])
 
 (define_mode_iterator VI48_AVX512F_AVX512VL
   [V4SI V8SI (V16SI "TARGET_AVX512F && TARGET_EVEX512")
@@ -2857,7 +2857,7 @@
        (div:VBF_AVX10_2
          (match_operand:VBF_AVX10_2 1 "register_operand")
          (match_operand:VBF_AVX10_2 2 "vector_operand")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
 {
   if (TARGET_RECIP_VEC_DIV
       && optimize_insn_for_speed_p ()
@@ -4850,7 +4850,7 @@
             (match_operand:<ssevecmode> 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
             (parallel [(const_int 0)]))]
          UNSPEC_COMX))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "v<unord>comx<ssemodesuffix>\t{<round_saeonly_op2>%1, %0|%0, %<iptr>1<round_saeonly_op2>}"
   [(set_attr "type" "ssecomi")
    (set_attr "prefix" "evex")
@@ -4885,7 +4885,7 @@
          (vec_select:BF
            (match_operand:V8BF 1 "nonimmediate_operand" "vm")
            (parallel [(const_int 0)]))))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vcomisbf16\t{%1, %0|%0, %1}"
   [(set_attr "prefix" "evex")
    (set_attr "type" "ssecomi")])
@@ -4921,7 +4921,7 @@
        (match_operator:<avx512fmaskmode> 1 ""
          [(match_operand:VBF_AVX10_2 2 "register_operand")
           (match_operand:VBF_AVX10_2 3 "nonimmediate_operand")]))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
 {
   bool ok = ix86_expand_mask_vec_cmp (operands[0], GET_CODE (operands[1]),
                                      operands[2], operands[3]);
@@ -5813,9 +5813,9 @@
    (V8HF "TARGET_AVX512FP16 && TARGET_AVX512VL")
    (V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL")
    (V32HF "TARGET_AVX512FP16 && TARGET_EVEX512")
-   (V8BF "TARGET_AVX10_2_256")
-   (V16BF "TARGET_AVX10_2_256")
-   (V32BF "TARGET_AVX10_2_512")])
+   (V8BF "TARGET_AVX10_2")
+   (V16BF "TARGET_AVX10_2")
+   (V32BF "TARGET_AVX10_2")])
 
 (define_expand "fma<mode>4"
   [(set (match_operand:FMAMODEM 0 "register_operand")
@@ -12095,7 +12095,7 @@
          (match_operand:V8_128 1 "reg_or_0_operand" "v,C")
          (const_int 1)))]
   "TARGET_AVX512FP16
-  || (TARGET_AVX10_2_256 && const0_operand (operands[1], <MODE>mode))"
+  || (TARGET_AVX10_2 && const0_operand (operands[1], <MODE>mode))"
   "@
     vmovsh\t{%2, %1, %0|%0, %1, %2}
     vmovw\t{%2, %0|%2, %0}"
@@ -23798,7 +23798,7 @@
            (match_operand:V64QI 2 "vector_operand" "vm")
            (match_operand:SI 3 "const_0_to_255_operand" "n")]
           UNSPEC_MPSADBW))]
-  "TARGET_AVX10_2_512"
+  "TARGET_AVX10_2"
   "vmpsadbw\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}"
   [(set_attr "length_immediate" "1")
    (set_attr "prefix" "evex")])
@@ -23810,7 +23810,7 @@
            (match_operand:VI1 2 "vector_operand" "vm")
            (match_operand:SI 3 "const_0_to_255_operand" "n")]
           UNSPEC_MPSADBW))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vmpsadbw\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}"
   [(set_attr "length_immediate" "1")
    (set_attr "prefix" "evex")
@@ -31445,8 +31445,8 @@
    (match_operand:<ssedvecmode> 3 "register_operand")]
   "TARGET_SSE2"
 {
-  if ((<MODE_SIZE> == 64 && TARGET_AVX10_2_512)
-      || (<MODE_SIZE> < 64 && (TARGET_AVXVNNIINT8 || TARGET_AVX10_2_256)))
+  if ((<MODE_SIZE> == 64 && TARGET_AVX10_2)
+      || (<MODE_SIZE> < 64 && (TARGET_AVXVNNIINT8 || TARGET_AVX10_2)))
     {
       operands[1] = lowpart_subreg (<ssedvecmode>mode,
                                    force_reg (<MODE>mode, operands[1]),
@@ -31493,8 +31493,8 @@
    (match_operand:<ssedvecmode> 3 "register_operand")]
   "TARGET_SSE2"
 {
-  if ((<MODE_SIZE> == 64 && TARGET_AVX10_2_512)
-      || (<MODE_SIZE> < 64 && (TARGET_AVXVNNIINT8 || TARGET_AVX10_2_256)))
+  if ((<MODE_SIZE> == 64 && TARGET_AVX10_2)
+      || (<MODE_SIZE> < 64 && (TARGET_AVXVNNIINT8 || TARGET_AVX10_2)))
     {
       operands[1] = lowpart_subreg (<ssedvecmode>mode,
                                    force_reg (<MODE>mode, operands[1]),
@@ -31541,7 +31541,7 @@
           (match_operand:VI4_AVX 2 "register_operand" "v")
           (match_operand:VI4_AVX 3 "nonimmediate_operand" "vm")]
          VPDOTPROD))]
-  "TARGET_AVXVNNIINT8 || TARGET_AVX10_2_256"
+  "TARGET_AVXVNNIINT8 || TARGET_AVX10_2"
   "vpdp<vpdotprodtype>\t{%3, %2, %0|%0, %2, %3}"
    [(set_attr "prefix" "maybe_evex")])
 
@@ -31552,7 +31552,7 @@
            (match_operand:V16SI 2 "register_operand" "v")
            (match_operand:V16SI 3 "nonimmediate_operand" "vm")]
           VPDOTPROD))]
-  "TARGET_AVX10_2_512"
+  "TARGET_AVX10_2"
   "vpdp<vpdotprodtype>\t{%3, %2, %0|%0, %2, %3}"
    [(set_attr "prefix" "evex")])
 
@@ -31566,7 +31566,7 @@
            VPDOTPROD)
          (match_dup 1)
          (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vpdp<vpdotprodtype>\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}"
    [(set_attr "prefix" "evex")])
 
@@ -31580,7 +31580,7 @@
            VPDOTPROD)
          (match_dup 5)
          (match_operand:<avx512fmaskmode> 4 "register_operand")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "operands[5] = CONST0_RTX (<MODE>mode);")
 
 (define_insn "*vpdp<vpdotprodtype>_<mode>_maskz"
@@ -31593,7 +31593,7 @@
            VPDOTPROD)
          (match_operand:VI4_AVX10_2 5 "const0_operand" "C")
          (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vpdp<vpdotprodtype>\t{%3, %2, %0%{%4%}%N5|%0%{%4%}%N5, %2, %3}"
    [(set_attr "prefix" "evex")])
 
@@ -31686,7 +31686,7 @@
            (match_operand:<ssePSmode> 2 "<round_nimm_predicate>" "<round_constraint>"))
          (float_truncate:<ssehalfvecmode>
            (match_operand:<ssePSmode> 1 "register_operand" "v"))))]
-  "TARGET_AVX10_2_256 && <round_mode512bit_condition>"
+  "TARGET_AVX10_2 && <round_mode512bit_condition>"
   "vcvt2ps2phx\t{<round_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_mask_op3>}")
 
 (define_mode_attr ssebvecmode
@@ -31708,7 +31708,7 @@
          [(match_operand:VHF_AVX10_2 1 "register_operand" "v")
           (match_operand:VHF_AVX10_2 2 "nonimmediate_operand" "vm")]
          UNSPEC_CONVERTFP8_PACK))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vcvt<convertfp8_pack>\t{%2, %1, %0<mask_operand3>|%0<mask_operand2>, %1, %2}"
   [(set_attr "prefix" "evex")])
 
@@ -31733,7 +31733,7 @@
             (match_operand:V8HF 2 "nonimmediate_operand")]
              UNSPEC_VCVTBIASPH2FP8_PACK)
          (match_dup 3)))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "operands[3] = CONST0_RTX (V8QImode);")
 
 (define_insn "*vcvt<biasph2fp8_pack>v8hf"
@@ -31744,7 +31744,7 @@
             (match_operand:V8HF 2 "nonimmediate_operand" "vm")]
              UNSPEC_VCVTBIASPH2FP8_PACK)
          (match_operand:V8QI 3 "const0_operand")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vcvt<biasph2fp8_pack>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "prefix" "evex")
    (set_attr "mode" "HF")])
@@ -31765,7 +31765,7 @@
                         (const_int 6) (const_int 7)]))
            (match_operand:QI 4 "register_operand" "C"))
          (match_dup 5)))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "operands[5] = CONST0_RTX (V8QImode);")
 
 (define_insn "*vcvt<biasph2fp8_pack>v8hf_mask"
@@ -31784,12 +31784,12 @@
                         (const_int 6) (const_int 7)]))
            (match_operand:QI 4 "register_operand" "Yk"))
          (match_operand:V8QI 5 "const0_operand")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vcvt<biasph2fp8_pack>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"
   [(set_attr "prefix" "evex")])
 
 (define_mode_iterator VHF_AVX10_2_2
-  [(V32HF "TARGET_AVX10_2_512") V16HF])
+  [(V32HF "TARGET_AVX10_2") V16HF])
 
 (define_insn "vcvt<biasph2fp8_pack><mode><mask_name>"
   [(set (match_operand:<ssebvecmode_2> 0 "register_operand" "=v")
@@ -31797,12 +31797,12 @@
          [(match_operand:<ssebvecmode> 1 "register_operand" "v")
           (match_operand:VHF_AVX10_2_2 2 "nonimmediate_operand" "vm")]
          UNSPEC_VCVTBIASPH2FP8_PACK))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vcvt<biasph2fp8_pack>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
   [(set_attr "prefix" "evex")])
 
 (define_mode_iterator VHF_256_512
-  [V16HF (V32HF "TARGET_AVX10_2_512")])
+  [V16HF (V32HF "TARGET_AVX10_2")])
 
 (define_mode_attr ph2fp8suff
   [(V32HF "") (V16HF "{y}") (V8HF "{x}")])
@@ -31824,7 +31824,7 @@
            [(match_operand:V8HF 1 "nonimmediate_operand")]
              UNSPEC_CONVERTPH2FP8)
          (match_dup 2)))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "operands[2] = CONST0_RTX (V8QImode);")
 
 (define_insn "*vcvt<convertph2fp8>v8hf"
@@ -31834,7 +31834,7 @@
            [(match_operand:V8HF 1 "nonimmediate_operand" "vm")]
              UNSPEC_CONVERTPH2FP8)
          (match_operand:V8QI 2 "const0_operand")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vcvt<convertph2fp8>{x}\t{%1, %0|%0, %1}"
   [(set_attr "prefix" "evex")
    (set_attr "mode" "HF")])
@@ -31854,7 +31854,7 @@
                         (const_int 6) (const_int 7)]))
            (match_operand:QI 3 "register_operand"))
          (match_dup 4)))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "operands[4] = CONST0_RTX (V8QImode);")
 
 (define_insn "*vcvt<convertph2fp8>v8hf_mask"
@@ -31872,7 +31872,7 @@
                         (const_int 6) (const_int 7)]))
            (match_operand:QI 3 "register_operand" "Yk"))
          (match_operand:V8QI 4 "const0_operand")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vcvt<convertph2fp8>{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
   [(set_attr "prefix" "evex")])
 
@@ -31881,7 +31881,7 @@
        (unspec:<ssebvecmode_2>
          [(match_operand:VHF_256_512 1 "nonimmediate_operand" "vm")]
          UNSPEC_CONVERTPH2FP8))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vcvt<convertph2fp8><ph2fp8suff>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "prefix" "evex")])
 
@@ -31890,7 +31890,7 @@
        (unspec:VHF_AVX10_2
          [(match_operand:<ssebvecmode_2> 1 "nonimmediate_operand" "vm")]
          UNSPEC_VCVTHF82PH))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vcvthf82ph\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "prefix" "evex")])
 
@@ -31912,7 +31912,7 @@
    (match_operand:VI2_AVX10_2 1 "register_operand")
    (match_operand:VI2_AVX10_2 2 "register_operand")
    (match_operand:<sseunpackmode> 3 "register_operand")]
-  "TARGET_AVXVNNIINT16 || TARGET_AVX10_2_256"
+  "TARGET_AVXVNNIINT16 || TARGET_AVX10_2"
 {
   operands[1] = lowpart_subreg (<sseunpackmode>mode,
                                 force_reg (<MODE>mode, operands[1]),
@@ -31930,7 +31930,7 @@
    (match_operand:VI2_AVX10_2 1 "register_operand")
    (match_operand:VI2_AVX10_2 2 "register_operand")
    (match_operand:<sseunpackmode> 3 "register_operand")]
-  "TARGET_AVXVNNIINT16 || TARGET_AVX10_2_256"
+  "TARGET_AVXVNNIINT16 || TARGET_AVX10_2"
 {
   operands[1] = lowpart_subreg (<sseunpackmode>mode,
                                 force_reg (<MODE>mode, operands[1]),
@@ -31950,7 +31950,7 @@
           (match_operand:VI4_AVX 2 "register_operand" "v")
           (match_operand:VI4_AVX 3 "nonimmediate_operand" "vm")]
          VPDPWPROD))]
-  "TARGET_AVXVNNIINT16 || TARGET_AVX10_2_256"
+  "TARGET_AVXVNNIINT16 || TARGET_AVX10_2"
   "vpdp<vpdpwprodtype>\t{%3, %2, %0|%0, %2, %3}"
    [(set_attr "prefix" "maybe_evex")])
 
@@ -31961,7 +31961,7 @@
            (match_operand:V16SI 2 "register_operand" "v")
            (match_operand:V16SI 3 "nonimmediate_operand" "vm")]
           VPDPWPROD))]
-  "TARGET_AVX10_2_512"
+  "TARGET_AVX10_2"
   "vpdp<vpdpwprodtype>\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "prefix" "evex")])
 
@@ -31975,7 +31975,7 @@
            VPDPWPROD)
          (match_dup 1)
          (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vpdp<vpdpwprodtype>\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}"
    [(set_attr "prefix" "evex")])
 
@@ -31989,7 +31989,7 @@
            VPDPWPROD)
          (match_dup 5)
          (match_operand:<avx512fmaskmode> 4 "register_operand")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "operands[5] = CONST0_RTX (<MODE>mode);")
 
 (define_insn "*vpdp<vpdpwprodtype>_<mode>_maskz"
@@ -32002,7 +32002,7 @@
            VPDPWPROD)
          (match_operand:VI4_AVX10_2 5 "const0_operand" "C")
          (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vpdp<vpdpwprodtype>\t{%3, %2, %0%{%4%}%N5|%0%{%4%}%N5, %2, %3}"
    [(set_attr "prefix" "evex")])
 
@@ -32013,7 +32013,7 @@
           (match_operand:VF1_AVX10_2 2 "register_operand" "v")
           (match_operand:VF1_AVX10_2 3 "nonimmediate_operand" "vm")]
           UNSPEC_VDPPHPS))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vdpphps\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "prefix" "evex")])
 
@@ -32027,7 +32027,7 @@
            UNSPEC_VDPPHPS)
          (match_dup 1)
          (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vdpphps\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}"
   [(set_attr "prefix" "evex")])
 
@@ -32037,7 +32037,7 @@
    (match_operand:VF1_AVX10_2 2 "register_operand")
    (match_operand:VF1_AVX10_2 3 "nonimmediate_operand")
    (match_operand:<avx512fmaskmode> 4 "register_operand")]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
 {
   emit_insn (gen_vdpphps_<mode>_maskz_1 (operands[0], operands[1],
     operands[2], operands[3], CONST0_RTX(<MODE>mode), operands[4]));
@@ -32054,7 +32054,7 @@
            UNSPEC_VDPPHPS)
          (match_operand:VF1_AVX10_2 4 "const0_operand" "C")
          (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vdpphps\t{%3, %2, %0%{%5%}%N4|%0%{%5%}%N4, %2, %3}"
   [(set_attr "prefix" "evex")])
 
@@ -32064,7 +32064,7 @@
        [(match_operand:VBF_AVX10_2 1 "register_operand" "v")
         (match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm")]
        UNSPEC_VSCALEFBF16))]
-   "TARGET_AVX10_2_256"
+   "TARGET_AVX10_2"
    "vscalefbf16\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
    [(set_attr "prefix" "evex")])
 
@@ -32073,14 +32073,14 @@
      (smaxmin:VBF_AVX10_2
        (match_operand:VBF_AVX10_2 1 "register_operand")
        (match_operand:VBF_AVX10_2 2 "nonimmediate_operand")))]
-  "TARGET_AVX10_2_256")
+  "TARGET_AVX10_2")
 
 (define_insn "avx10_2_<code>bf16_<mode><mask_name>"
    [(set (match_operand:VBF_AVX10_2 0 "register_operand" "=v")
       (smaxmin:VBF_AVX10_2
         (match_operand:VBF_AVX10_2 1 "register_operand" "v")
         (match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm")))]
-   "TARGET_AVX10_2_256"
+   "TARGET_AVX10_2"
    "v<maxmin_float>bf16\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
    [(set_attr "prefix" "evex")
     (set_attr "mode" "<MODE>")])
@@ -32090,7 +32090,7 @@
       (plusminusmultdiv:VBF_AVX10_2
        (match_operand:VBF_AVX10_2 1 "register_operand" "v")
        (match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm")))]
-   "TARGET_AVX10_2_256"
+   "TARGET_AVX10_2"
    "v<insn>bf16\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
    [(set_attr "prefix" "evex")])
 
@@ -32100,7 +32100,7 @@
    (match_operand:VBF_AVX10_2 2 "nonimmediate_operand")
    (match_operand:VBF_AVX10_2 3 "nonimmediate_operand")
    (match_operand:<avx512fmaskmode> 4 "register_operand")]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   {
     emit_insn (gen_avx10_2_fmaddbf16_<mode>_maskz_1 (operands[0], operands[1],
                                                     operands[2], operands[3],
@@ -32115,7 +32115,7 @@
            (match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "%0,0,v")
            (match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm,v,vm")
            (match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "v,vm,0")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "@
    vfmadd132bf16\t{%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2}
    vfmadd213bf16\t{%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3}
@@ -32133,7 +32133,7 @@
             (match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "v,vm"))
          (match_dup 1)
          (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk,Yk")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "@
    vfmadd132bf16\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2}
    vfmadd213bf16\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}"
@@ -32150,7 +32150,7 @@
             (match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "0"))
          (match_dup 3)
          (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vfmadd231bf16\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}"
   [(set_attr "prefix" "evex")
    (set_attr "type" "ssemuladd")
@@ -32162,7 +32162,7 @@
    (match_operand:VBF_AVX10_2 2 "nonimmediate_operand")
    (match_operand:VBF_AVX10_2 3 "nonimmediate_operand")
    (match_operand:<avx512fmaskmode> 4 "register_operand")]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   {
     emit_insn (gen_avx10_2_fnmaddbf16_<mode>_maskz_1 (operands[0], operands[1],
                                                      operands[2], operands[3],
@@ -32178,7 +32178,7 @@
              (match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "%0,0,v"))
            (match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm,v,vm")
            (match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "v,vm,0")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "@
    vfnmadd132bf16\t{%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2}
    vfnmadd213bf16\t{%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3}
@@ -32197,7 +32197,7 @@
            (match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "v,vm"))
          (match_dup 1)
          (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk,Yk")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "@
    vfnmadd132bf16\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2}
    vfnmadd213bf16\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}"
@@ -32215,7 +32215,7 @@
            (match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "0"))
          (match_dup 3)
          (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vfnmadd231bf16\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}"
   [(set_attr "prefix" "evex")
    (set_attr "type" "ssemuladd")
@@ -32227,7 +32227,7 @@
    (match_operand:VBF_AVX10_2 2 "nonimmediate_operand")
    (match_operand:VBF_AVX10_2 3 "nonimmediate_operand")
    (match_operand:<avx512fmaskmode> 4 "register_operand")]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   {
     emit_insn (gen_avx10_2_fmsubbf16_<mode>_maskz_1 (operands[0], operands[1],
                                                     operands[2], operands[3],
@@ -32243,7 +32243,7 @@
            (match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm,v,vm")
            (neg:VBF_AVX10_2
              (match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "v,vm,0"))))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "@
    vfmsub132bf16\t{%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2}
    vfmsub213bf16\t{%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3}
@@ -32262,7 +32262,7 @@
              (match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "v,vm")))
          (match_dup 1)
          (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk,Yk")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "@
    vfmsub132bf16\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2}
    vfmsub213bf16\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}"
@@ -32280,7 +32280,7 @@
              (match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "0")))
          (match_dup 3)
          (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vfmsub231bf16\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}"
   [(set_attr "prefix" "evex")
    (set_attr "type" "ssemuladd")
@@ -32292,7 +32292,7 @@
    (match_operand:VBF_AVX10_2 2 "nonimmediate_operand")
    (match_operand:VBF_AVX10_2 3 "nonimmediate_operand")
    (match_operand:<avx512fmaskmode> 4 "register_operand")]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   {
     emit_insn (gen_avx10_2_fnmsubbf16_<mode>_maskz_1 (operands[0], operands[1],
                                                      operands[2], operands[3],
@@ -32309,7 +32309,7 @@
            (match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm,v,vm")
            (neg:VBF_AVX10_2
              (match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "v,vm,0"))))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "@
    vfnmsub132bf16\t{%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2}
    vfnmsub213bf16\t{%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3}
@@ -32329,7 +32329,7 @@
              (match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "v,vm")))
          (match_dup 1)
          (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk,Yk")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "@
    vfnmsub132bf16\t{%2, %3, %0%{%4%}|%0%{%4%}, %3, %2}
    vfnmsub213bf16\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}"
@@ -32348,7 +32348,7 @@
              (match_operand:VBF_AVX10_2 3 "nonimmediate_operand" "0")))
          (match_dup 3)
          (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vfnmsub231bf16\t{%2, %1, %0%{%4%}|%0%{%4%}, %1, %2}"
   [(set_attr "prefix" "evex")
    (set_attr "type" "ssemuladd")
@@ -32359,7 +32359,7 @@
         (unspec:VBF_AVX10_2
           [(match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "vm")]
          UNSPEC_RSQRT))]
-   "TARGET_AVX10_2_256"
+   "TARGET_AVX10_2"
    "vrsqrtbf16\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "prefix" "evex")])
 
@@ -32367,7 +32367,7 @@
    [(set (match_operand:VBF_AVX10_2 0 "register_operand" "=v")
         (sqrt:VBF_AVX10_2
           (match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "vm")))]
-   "TARGET_AVX10_2_256"
+   "TARGET_AVX10_2"
    "vsqrtbf16\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "prefix" "evex")])
 
@@ -32376,7 +32376,7 @@
         (unspec:VBF_AVX10_2
           [(match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "vm")]
          UNSPEC_RCP))]
-   "TARGET_AVX10_2_256"
+   "TARGET_AVX10_2"
    "vrcpbf16\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "prefix" "evex")])
 
@@ -32385,7 +32385,7 @@
         (unspec:VBF_AVX10_2
           [(match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "vm")]
          UNSPEC_GETEXP))]
-   "TARGET_AVX10_2_256"
+   "TARGET_AVX10_2"
    "vgetexpbf16\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "prefix" "evex")])
 
@@ -32405,7 +32405,7 @@
           [(match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "vm")
            (match_operand:SI 2 "const_0_to_255_operand")]
          BF16IMMOP))]
-   "TARGET_AVX10_2_256"
+   "TARGET_AVX10_2"
    "v<bf16immop>bf16\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
    [(set_attr "prefix" "evex")])
 
@@ -32415,7 +32415,7 @@
           [(match_operand:VBF_AVX10_2 1 "nonimmediate_operand" "vm")
            (match_operand 2 "const_0_to_255_operand")]
          UNSPEC_VFPCLASSBF16))]
-   "TARGET_AVX10_2_256"
+   "TARGET_AVX10_2"
    "vfpclassbf16<vecmemsuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
    [(set_attr "prefix" "evex")])
 
@@ -32426,7 +32426,7 @@
            (match_operand:VBF_AVX10_2 2 "nonimmediate_operand" "vm")
            (match_operand 3 "const_0_to_31_operand" "n")]
          UNSPEC_PCMP))]
-   "TARGET_AVX10_2_256"
+   "TARGET_AVX10_2"
    "vcmpbf16\t{%3, %2, %1, %0<mask_scalar_merge_operand4>|%0<mask_scalar_merge_operand4>, %1, %2, %3}"
    [(set_attr "prefix" "evex")])
 
@@ -32463,7 +32463,7 @@
        (unspec:<sseintvecmode>
          [(match_operand:VBF_AVX10_2 1 "vector_operand" "vm")]
          UNSPEC_CVT_BF16_IBS_ITER))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
  "vcvt<sat_cvt_trunc_prefix>bf162i<sat_cvt_sign_prefix>bs\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
  [(set_attr "type" "ssecvt")
   (set_attr "prefix" "evex")
@@ -32478,7 +32478,7 @@
        (unspec:<sseintvecmode>
          [(match_operand:VHF_AVX10_2 1 "<round_nimm_predicate>" "<round_constraint>")]
          UNSPEC_CVT_PH_IBS_ITER))]
- "TARGET_AVX10_2_256 && <round_mode512bit_condition>"
+ "TARGET_AVX10_2 && <round_mode512bit_condition>"
  "vcvtph2i<sat_cvt_sign_prefix>bs\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
  [(set_attr "type" "ssecvt")
   (set_attr "prefix" "evex")
@@ -32493,7 +32493,7 @@
        (unspec:<sseintvecmode>
          [(match_operand:VHF_AVX10_2 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
          UNSPEC_CVTT_PH_IBS_ITER))]
- "TARGET_AVX10_2_256 && <round_saeonly_mode512bit_condition>"
+ "TARGET_AVX10_2 && <round_saeonly_mode512bit_condition>"
  "vcvttph2i<sat_cvt_sign_prefix>bs\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
  [(set_attr "type" "ssecvt")
   (set_attr "prefix" "evex")
@@ -32508,7 +32508,7 @@
        (unspec:<sseintvecmode>
          [(match_operand:VF1_AVX10_2 1 "<round_nimm_predicate>" "<round_constraint>")]
          UNSPEC_CVT_PS_IBS_ITER))]
- "TARGET_AVX10_2_256 && <round_mode512bit_condition>"
+ "TARGET_AVX10_2 && <round_mode512bit_condition>"
  "vcvtps2i<sat_cvt_sign_prefix>bs\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
  [(set_attr "type" "ssecvt")
   (set_attr "prefix" "evex")
@@ -32523,7 +32523,7 @@
        (unspec:<sseintvecmode>
          [(match_operand:VF1_AVX10_2 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
          UNSPEC_CVTT_PS_IBS_ITER))]
- "TARGET_AVX10_2_256 && <round_saeonly_mode512bit_condition>"
+ "TARGET_AVX10_2 && <round_saeonly_mode512bit_condition>"
  "vcvttps2i<sat_cvt_sign_prefix>bs\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
  [(set_attr "type" "ssecvt")
   (set_attr "prefix" "evex")
@@ -32542,7 +32542,7 @@
        (unspec:<VEC_GATHER_IDXSI>
          [(match_operand:VF1_VF2_AVX10_2 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
          UNSPEC_SAT_CVT_DS_SIGN_ITER))]
- "TARGET_AVX10_2_256 && <round_saeonly_mode512bit_condition>"
+ "TARGET_AVX10_2 && <round_saeonly_mode512bit_condition>"
  "vcvtt<castmode>2<sat_cvt_sign_prefix>dqs<pd2dqssuff>\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
  [(set_attr "type" "ssecvt")
   (set_attr "prefix" "evex")
@@ -32553,7 +32553,7 @@
        (unspec:<VEC_GATHER_IDXDI>
          [(match_operand:VF2_AVX10_2 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
          UNSPEC_SAT_CVT_DS_SIGN_ITER))]
- "TARGET_AVX10_2_256 && <round_saeonly_mode512bit_condition>"
+ "TARGET_AVX10_2 && <round_saeonly_mode512bit_condition>"
  "vcvttpd2<sat_cvt_sign_prefix>qqs\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
  [(set_attr "type" "ssecvt")
   (set_attr "prefix" "evex")
@@ -32564,7 +32564,7 @@
        (unspec:VI8_AVX10_2
          [(match_operand:<vpckfloat_temp_mode> 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")]
          UNSPEC_SAT_CVT_DS_SIGN_ITER))]
- "TARGET_AVX10_2_256 && <round_saeonly_mode512bit_condition>"
+ "TARGET_AVX10_2 && <round_saeonly_mode512bit_condition>"
  "vcvttps2<sat_cvt_sign_prefix>qqs\t{<round_saeonly_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_saeonly_mask_op2>}"
  [(set_attr "type" "ssecvt")
   (set_attr "prefix" "evex")
@@ -32577,7 +32577,7 @@
       (match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
       (parallel [(const_int 0)]))]
     UNSPEC_SAT_CVT_DS_SIGN_ITER))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
  "vcvttsd2<sat_cvt_sign_prefix>sis\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}"
  [(set_attr "type" "ssecvt")
  (set_attr "prefix" "evex")
@@ -32590,7 +32590,7 @@
       (match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
       (parallel [(const_int 0)]))]
     UNSPEC_SAT_CVT_DS_SIGN_ITER))]
- "TARGET_AVX10_2_256"
+ "TARGET_AVX10_2"
  "vcvttss2<sat_cvt_sign_prefix>sis\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}"
  [(set_attr "type" "ssecvt")
  (set_attr "prefix" "evex")
@@ -32603,7 +32603,7 @@
        (match_operand:VBF_AVX10_2 2 "bcst_vector_operand" "vmBr")
        (match_operand:SI 3 "const_0_to_255_operand")]
        UNSPEC_MINMAXBF16))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vminmaxbf16\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}"
   [(set_attr "prefix" "evex")
    (set_attr "mode" "<sseinsnmode>")])
@@ -32615,7 +32615,7 @@
        (match_operand:VFH_AVX10_2 2 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")
        (match_operand:SI 3 "const_0_to_255_operand")]
       UNSPEC_MINMAX))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vminmax<ssemodesuffix>\t{%3, <round_saeonly_mask_op4>%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2<round_saeonly_mask_op4>, %3}"
   [(set_attr "prefix" "evex")
    (set_attr "mode" "<MODE>")])
@@ -32630,7 +32630,7 @@
         UNSPEC_MINMAX)
       (match_dup 1)
       (const_int 1)))]
-  "TARGET_AVX10_2_256"
+  "TARGET_AVX10_2"
   "vminmax<ssescalarmodesuffix>\t{%3, <round_saeonly_scalar_mask_op4>%2, %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %2<round_saeonly_scalar_mask_op4>, %3}"
   [(set_attr "prefix" "evex")
    (set_attr "mode" "<ssescalarmode>")])
@@ -32640,7 +32640,7 @@
        (unspec:VI1248_AVX10_2
          [(match_operand:VI1248_AVX10_2 1 "memory_operand" "m")]
          UNSPEC_VMOVRS))]
-  "TARGET_AVX10_2_256 && TARGET_MOVRS"
+  "TARGET_AVX10_2 && TARGET_MOVRS"
   "vmovrs<ssemodesuffix>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "type" "ssemov")
    (set_attr "prefix" "evex")

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 9f8a590a30166143196f5bb4524b5e880a67c426..522d51a7dee29245ddac3e7b17386639a9434d28 100644 (file)
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -6648,16 +6648,7 @@ Disable the generation of the AVX10.1 instructions.
 @cindex @code{target("avx10.2")} function attribute, x86
 @item avx10.2
 @itemx no-avx10.2
-Enable the generation of the AVX10.2 instructions with 512 bit support.
-Disable the generation of the AVX10.2 instructions.
-
-@cindex @code{target("avx10.2-256")} function attribute, x86
-@item avx10.2-256
-Enable the generation of the AVX10.2 instructions with 256 bit support.
-
-@cindex @code{target("avx10.2-512")} function attribute, x86
-@item avx10.2-512
-Enable the generation of the AVX10.2 instructions with 512 bit support.
+Enable/Disable the generation of the AVX10.2 instructions.
 
 @cindex @code{target("amx-avx512")} function attribute, x86
 @item amx-avx512

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 36b252be387ff70c99ec60e045f9b2b3caad8418..3f5b7e9f36685093f2b84b859881703eee784a1c 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1489,8 +1489,8 @@ See RS/6000 and PowerPC Options.
 -mamx-tile  -mamx-int8  -mamx-bf16 -muintr -mhreset -mavxvnni -mamx-fp8
 -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16
 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf
--musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512 -mevex512 -mavx10.2 -mavx10.2-256
--mavx10.2-512 -mamx-avx512 -mamx-tf32 -mamx-transpose -mmovrs -mamx-movrs
+-musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512 -mevex512 -mavx10.2
+-mamx-avx512 -mamx-tf32 -mamx-transpose -mmovrs -mamx-movrs
 -mcldemote  -mms-bitfields  -mno-align-stringops  -minline-all-stringops
 -minline-stringops-dynamically  -mstringop-strategy=@var{alg}
 -mkl -mwidekl
@@ -35908,12 +35908,6 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
 @opindex mavx10.2
 @itemx -mavx10.2
 @need 200
-@opindex mavx10.2-256
-@itemx -mavx10.2-256
-@need 200
-@opindex mavx10.2-512
-@itemx -mavx10.2-512
-@need 200
 @opindex mamx-avx512
 @itemx -mamx-avx512
 @need 200

diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 84fd2735c677454f5e94e180692e820c7c17d1e0..f0912cf262d4fdf3f8dc4dfd98511f857ef55b90 100644 (file)
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2630,13 +2630,7 @@ Target supports the execution of @code{avx10.1-256} instructions.
 Target supports the execution of @code{avx10.1-512} instructions.
 
 @item avx10.2
-Target supports the execution of @code{avx10.2-512} instructions.
-
-@item avx10.2-256
-Target supports the execution of @code{avx10.2-256} instructions.
-
-@item avx10.2-512
-Target supports the execution of @code{avx10.2-512} instructions.
+Target supports the execution of @code{avx10.2} instructions.
 
 @item avx2
 Target supports compiling @code{avx2} instructions.