media: qcom: camss: Add Qualcomm SM8650 CAMSS support

Add the basic support of CAMSS IP on Qualcomm SM8650 SoC powered boards.

SM8650 CAMSS provides:
- 6 x CSIPHY,
- 3 x CSID, 2 x CSID Lite,
- 3 x VFE, 2 x VFE Lite.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>

diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 55fb7547f84f1d9a7ea282fc731af8df14fcf54a..ffa695a9cd94caa47dbc477fdba3a349d2b5fac3 100644 (file)
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -348,6 +348,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
        case CAMSS_8300:
        case CAMSS_845:
        case CAMSS_8550:
+       case CAMSS_8650:
        case CAMSS_8775P:
        case CAMSS_X1E80100:
                switch (sink_code) {
@@ -1996,6 +1997,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
        case CAMSS_8300:
        case CAMSS_845:
        case CAMSS_8550:
+       case CAMSS_8650:
        case CAMSS_8775P:
        case CAMSS_X1E80100:
                ret = 16;

diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 0705e92541fc2350eb30bb18c9a972fac137181f..0c919a311f11d3912c0163c8073d33c91a93d938 100644 (file)
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -2617,6 +2617,317 @@ static const struct resources_icc icc_res_sm8550[] = {
        },
 };
 
+static const struct camss_subdev_resources csiphy_res_sm8650[] = {
+       /* CSIPHY0 */
+       {
+               .regulators = { "vdd-csiphy01-0p9", "vdd-csiphy01-1p2", },
+               .clock = { "csiphy0", "csiphy0_timer" },
+               .clock_rate = { { 400000000 },
+                               { 400000000 } },
+               .reg = { "csiphy0" },
+               .interrupt = { "csiphy0" },
+               .csiphy = {
+                       .id = 0,
+                       .hw_ops = &csiphy_ops_3ph_1_0,
+                       .formats = &csiphy_formats_sdm845,
+               },
+       },
+       /* CSIPHY1 */
+       {
+               .regulators = { "vdd-csiphy01-0p9", "vdd-csiphy01-1p2", },
+               .clock = { "csiphy1", "csiphy1_timer" },
+               .clock_rate = { { 400000000 },
+                               { 400000000 } },
+               .reg = { "csiphy1" },
+               .interrupt = { "csiphy1" },
+               .csiphy = {
+                       .id = 1,
+                       .hw_ops = &csiphy_ops_3ph_1_0,
+                       .formats = &csiphy_formats_sdm845,
+               },
+       },
+       /* CSIPHY2 */
+       {
+               .regulators = { "vdd-csiphy24-0p9", "vdd-csiphy24-1p2", },
+               .clock = { "csiphy2", "csiphy2_timer" },
+               .clock_rate = { { 400000000 },
+                               { 400000000 } },
+               .reg = { "csiphy2" },
+               .interrupt = { "csiphy2" },
+               .csiphy = {
+                       .id = 2,
+                       .hw_ops = &csiphy_ops_3ph_1_0,
+                       .formats = &csiphy_formats_sdm845,
+               },
+       },
+       /* CSIPHY3 */
+       {
+               .regulators = { "vdd-csiphy35-0p9", "vdd-csiphy35-1p2", },
+               .clock = { "csiphy3", "csiphy3_timer" },
+               .clock_rate = { { 400000000 },
+                               { 400000000 } },
+               .reg = { "csiphy3" },
+               .interrupt = { "csiphy3" },
+               .csiphy = {
+                       .id = 3,
+                       .hw_ops = &csiphy_ops_3ph_1_0,
+                       .formats = &csiphy_formats_sdm845,
+               },
+       },
+       /* CSIPHY4 */
+       {
+               .regulators = { "vdd-csiphy24-0p9", "vdd-csiphy24-1p2", },
+               .clock = { "csiphy4", "csiphy4_timer" },
+               .clock_rate = { { 400000000 },
+                               { 400000000 } },
+               .reg = { "csiphy4" },
+               .interrupt = { "csiphy4" },
+               .csiphy = {
+                       .id = 4,
+                       .hw_ops = &csiphy_ops_3ph_1_0,
+                       .formats = &csiphy_formats_sdm845,
+               },
+       },
+       /* CSIPHY5 */
+       {
+               .regulators = { "vdd-csiphy35-0p9", "vdd-csiphy35-1p2", },
+               .clock = { "csiphy5", "csiphy5_timer" },
+               .clock_rate = { { 400000000 },
+                               { 400000000 } },
+               .reg = { "csiphy5" },
+               .interrupt = { "csiphy5" },
+               .csiphy = {
+                       .id = 5,
+                       .hw_ops = &csiphy_ops_3ph_1_0,
+                       .formats = &csiphy_formats_sdm845,
+               },
+       },
+};
+
+static const struct camss_subdev_resources csid_res_sm8650[] = {
+       /* CSID0 */
+       {
+               .regulators = { },
+               .clock = { "csid", "csiphy_rx" },
+               .clock_rate = { { 400000000 },
+                               { 400000000, 480000000 } },
+               .reg = { "csid0" },
+               .interrupt = { "csid0" },
+               .csid = {
+                       .parent_dev_ops = &vfe_parent_dev_ops,
+                       .hw_ops = &csid_ops_gen3,
+                       .formats = &csid_formats_gen2,
+               },
+       },
+       /* CSID1 */
+       {
+               .regulators = { },
+               .clock = { "csid", "csiphy_rx" },
+               .clock_rate = { { 400000000 },
+                               { 400000000, 480000000 } },
+               .reg = { "csid1" },
+               .interrupt = { "csid1" },
+               .csid = {
+                       .parent_dev_ops = &vfe_parent_dev_ops,
+                       .hw_ops = &csid_ops_gen3,
+                       .formats = &csid_formats_gen2,
+               },
+       },
+       /* CSID2 */
+       {
+               .regulators = { },
+               .clock = { "csid", "csiphy_rx" },
+               .clock_rate = { { 400000000 },
+                               { 400000000, 480000000 } },
+               .reg = { "csid2" },
+               .interrupt = { "csid2" },
+               .csid = {
+                       .parent_dev_ops = &vfe_parent_dev_ops,
+                       .hw_ops = &csid_ops_gen3,
+                       .formats = &csid_formats_gen2,
+               },
+       },
+       /* CSID3 lite */
+       {
+               .regulators = { },
+               .clock = { "vfe_lite_ahb", "vfe_lite_csid", "vfe_lite_cphy_rx" },
+               .clock_rate = { { 0 },
+                               { 400000000, 480000000 },
+                               { 0 } },
+               .reg = { "csid_lite0" },
+               .interrupt = { "csid_lite0" },
+               .csid = {
+                       .is_lite = true,
+                       .parent_dev_ops = &vfe_parent_dev_ops,
+                       .hw_ops = &csid_ops_gen3,
+                       .formats = &csid_formats_gen2,
+               },
+       },
+       /* CSID4 lite */
+       {
+               .regulators = { },
+               .clock = { "vfe_lite_ahb", "vfe_lite_csid", "vfe_lite_cphy_rx" },
+               .clock_rate = { { 0 },
+                               { 400000000, 480000000 },
+                               { 0 } },
+               .reg = { "csid_lite1" },
+               .interrupt = { "csid_lite1" },
+               .csid = {
+                       .is_lite = true,
+                       .parent_dev_ops = &vfe_parent_dev_ops,
+                       .hw_ops = &csid_ops_gen3,
+                       .formats = &csid_formats_gen2,
+               },
+       },
+};
+
+static const struct camss_subdev_resources vfe_res_sm8650[] = {
+       /* VFE0 */
+       {
+               .regulators = { },
+               .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
+                          "camnoc_axi", "vfe0_fast_ahb", "vfe0", "cpas_vfe0",
+                          "qdss_debug_xo",
+               },
+               .clock_rate = { { 0 },
+                               { 80000000 },
+                               { 300000000, 400000000 },
+                               { 300000000, 400000000 },
+                               { 0 },
+                               { 466000000, 594000000, 675000000, 785000000 },
+                               { 0 },
+                               { 0 },
+               },
+               .reg = { "vfe0" },
+               .interrupt = { "vfe0" },
+               .vfe = {
+                       .line_num = 3,
+                       .has_pd = true,
+                       .pd_name = "ife0",
+                       .hw_ops = &vfe_ops_gen3,
+                       .formats_rdi = &vfe_formats_rdi_845,
+                       .formats_pix = &vfe_formats_pix_845
+               },
+       },
+       /* VFE1 */
+       {
+               .regulators = { },
+               .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
+                          "camnoc_axi", "vfe1_fast_ahb", "vfe1", "cpas_vfe1",
+                          "qdss_debug_xo",
+               },
+               .clock_rate = { { 0 },
+                               { 80000000 },
+                               { 300000000, 400000000 },
+                               { 300000000, 400000000 },
+                               { 0 },
+                               { 466000000, 594000000, 675000000, 785000000 },
+                               { 0 },
+                               { 0 },
+               },
+               .reg = { "vfe1" },
+               .interrupt = { "vfe1" },
+               .vfe = {
+                       .line_num = 3,
+                       .has_pd = true,
+                       .pd_name = "ife1",
+                       .hw_ops = &vfe_ops_gen3,
+                       .formats_rdi = &vfe_formats_rdi_845,
+                       .formats_pix = &vfe_formats_pix_845
+               },
+       },
+       /* VFE2 */
+       {
+               .regulators = { },
+               .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb",
+                          "camnoc_axi", "vfe2_fast_ahb", "vfe2", "cpas_vfe2",
+                          "qdss_debug_xo",
+               },
+               .clock_rate = { { 0 },
+                               { 80000000 },
+                               { 300000000, 400000000 },
+                               { 300000000, 400000000 },
+                               { 0 },
+                               { 466000000, 594000000, 675000000, 785000000 },
+                               { 0 },
+                               { 0 },
+               },
+               .reg = { "vfe2" },
+               .interrupt = { "vfe2" },
+               .vfe = {
+                       .line_num = 3,
+                       .has_pd = true,
+                       .pd_name = "ife2",
+                       .hw_ops = &vfe_ops_gen3,
+                       .formats_rdi = &vfe_formats_rdi_845,
+                       .formats_pix = &vfe_formats_pix_845
+               },
+       },
+       /* VFE3 lite */
+       {
+               .regulators = { },
+               .clock = { "gcc_axi_hf", "cpas_ahb", "camnoc_axi",
+                          "vfe_lite_ahb", "vfe_lite", "cpas_vfe_lite",
+                          "qdss_debug_xo",
+               },
+               .clock_rate = { { 0 },
+                               { 80000000 },
+                               { 300000000, 400000000 },
+                               { 0 },
+                               { 400000000, 480000000 },
+                               { 0 },
+                               { 0 },
+               },
+               .reg = { "vfe_lite0" },
+               .interrupt = { "vfe_lite0" },
+               .vfe = {
+                       .line_num = 4,
+                       .is_lite = true,
+                       .hw_ops = &vfe_ops_gen3,
+                       .formats_rdi = &vfe_formats_rdi_845,
+                       .formats_pix = &vfe_formats_pix_845
+               },
+       },
+       /* VFE4 lite */
+       {
+               .regulators = { },
+               .clock = { "gcc_axi_hf", "cpas_ahb", "camnoc_axi",
+                          "vfe_lite_ahb", "vfe_lite", "cpas_vfe_lite",
+                          "qdss_debug_xo",
+               },
+               .clock_rate = { { 0 },
+                               { 80000000 },
+                               { 300000000, 400000000 },
+                               { 0 },
+                               { 400000000, 480000000 },
+                               { 0 },
+                               { 0 },
+               },
+               .reg = { "vfe_lite1" },
+               .interrupt = { "vfe_lite1" },
+               .vfe = {
+                       .line_num = 4,
+                       .is_lite = true,
+                       .hw_ops = &vfe_ops_gen3,
+                       .formats_rdi = &vfe_formats_rdi_845,
+                       .formats_pix = &vfe_formats_pix_845
+               },
+       },
+};
+
+static const struct resources_icc icc_res_sm8650[] = {
+       {
+               .name = "ahb",
+               .icc_bw_tbl.avg = 38400,
+               .icc_bw_tbl.peak = 76800,
+       },
+       {
+               .name = "hf_mnoc",
+               .icc_bw_tbl.avg = 2097152,
+               .icc_bw_tbl.peak = 2097152,
+       },
+};
+
 static const struct camss_subdev_resources csiphy_res_8300[] = {
        /* CSIPHY0 */
        {
@@ -4452,6 +4763,20 @@ static const struct camss_resources sm8550_resources = {
        .vfe_num = ARRAY_SIZE(vfe_res_8550),
 };
 
+static const struct camss_resources sm8650_resources = {
+       .version = CAMSS_8650,
+       .pd_name = "top",
+       .csiphy_res = csiphy_res_sm8650,
+       .csid_res = csid_res_sm8650,
+       .csid_wrapper_res = &csid_wrapper_res_sm8550,
+       .vfe_res = vfe_res_sm8650,
+       .icc_res = icc_res_sm8650,
+       .icc_path_num = ARRAY_SIZE(icc_res_sm8650),
+       .csiphy_num = ARRAY_SIZE(csiphy_res_sm8650),
+       .csid_num = ARRAY_SIZE(csid_res_sm8650),
+       .vfe_num = ARRAY_SIZE(vfe_res_sm8650),
+};
+
 static const struct camss_resources x1e80100_resources = {
        .version = CAMSS_X1E80100,
        .pd_name = "top",
@@ -4480,6 +4805,7 @@ static const struct of_device_id camss_dt_match[] = {
        { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
        { .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
        { .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
+       { .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
        { .compatible = "qcom,x1e80100-camss", .data = &x1e80100_resources },
        { }
 };

diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index 901f84efaf7d2b713213b69eee653cc5af7f58d4..205a37bb1ade92dd77ff4386428196c33e52b2dc 100644 (file)
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -89,6 +89,7 @@ enum camss_version {
        CAMSS_8300,
        CAMSS_845,
        CAMSS_8550,
+       CAMSS_8650,
        CAMSS_8775P,
        CAMSS_X1E80100,
 };