+2019-09-27 Paul A. Clarke <pc@us.ibm.com>
+
+ * sysdeps/powerpc/fpu/fenv_libc.h:
+ (__TEST_AND_ENTER_NON_STOP): New.
+ (__TEST_AND_EXIT_NON_STOP): New.
+ * sysdeps/powerpc/fpu/fenv_private.h
+ (_FPU_ALL_TRAPS): Delete, replace with FPSCR_ENABLES_MASK.
+ (_FPU_MASK_RN): Delete.
+ (_FPU_MASK_NOT_RN_NI): Delete.
+ (_FPU_MASK_TRAPS_RN): Delete, replace with ~FPSCR_CONTROL_MASK.
+ (_FPU_MASK_FRAC_INEX_RET_CC): Delete, replace with ~FPSCR_STATUS_MASK.
+ (__libc_feholdbits_ppc): Delete, move code into
+ libc_feholdexcept_setround_ppc.
+ (libc_feholdexcept_ppc): Delete.
+ (libc_fesetround_ppc): Delete.
+ (libc_fetestexcept_ppc): Delete.
+ (libc_feholdsetround_ppc): Delete.
+ (__libc_femergeenv_ppc): Use __TEST_AND_ENTER/EXIT_NON_STOP.
+ (libc_feholdsetround_noex_ppc_ctx): Likewise.
+ (libc_feupdateenv_test_ppc): Use FPSCR defines.
+ * sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Use
+ __TEST_AND_ENTER_NON_STOP.
+ * sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Likewise.
+ * sysdeps/powerpc/fpu/feholdexcpt.c (__feholdexcept): Likewise.
+ * sysdeps/powerpc/fpu/fesetenv.c (__fesetenv): Likewise.
+ * sysdeps/powerpc/fpu/fesetmode.c (fesetmode): Likewise.
+ * sysdeps/powerpc/fpu/feupdateenv.c (__feupdateenv): Likewise.
+ (_FPU_MASK_ALL): Delete.
+
2019-09-19 Paul A. Clarke <pc@us.ibm.com>
* sysdeps/powerpc/fpu/fenv_libc.h (fegetenv_and_set_rn): New.
if (fe.l != curr.l)
fesetenv_mode (fe.fenv);
- if (new == 0 && result != 0)
- (void)__fe_mask_env ();
+ __TEST_AND_ENTER_NON_STOP (-1ULL, fe.l);
return result;
}
if (fe.l != curr.l)
fesetenv_mode (fe.fenv);
- if (new != 0 && result == 0)
- (void) __fe_nomask_env_priv ();
+ __TEST_AND_EXIT_NON_STOP (0ULL, fe.l);
return result;
}
#include <fenv_libc.h>
#include <fpu_control.h>
-#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM)
int
__feholdexcept (fenv_t *envp)
if (new.l == old.l)
return 0;
- /* If the old env had any enabled exceptions, then mask SIGFPE in the
- MSR FE0/FE1 bits. This may allow the FPU to run faster because it
- always takes the default action and can not generate SIGFPE. */
- if ((old.l & _FPU_MASK_ALL) != 0)
- (void)__fe_mask_env ();
+ __TEST_AND_ENTER_NON_STOP (old.l, 0ULL);
/* Put the new state in effect. */
fesetenv_register (new.fenv);
extern const fenv_t *__fe_mask_env (void) attribute_hidden;
+/* If the old env had any enabled exceptions and the new env has no enabled
+ exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
+ FPU to run faster because it always takes the default action and can not
+ generate SIGFPE. */
+#define __TEST_AND_ENTER_NON_STOP(old, new) \
+ do { \
+ if (((old) & FPSCR_ENABLES_MASK) != 0 && ((new) & FPSCR_ENABLES_MASK) == 0) \
+ (void) __fe_mask_env (); \
+ } while (0)
+
+/* If the old env has no enabled exceptions and the new env has any enabled
+ exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the
+ hardware into "precise mode" and may cause the FPU to run slower on some
+ hardware. */
+#define __TEST_AND_EXIT_NON_STOP(old, new) \
+ do { \
+ if (((old) & FPSCR_ENABLES_MASK) == 0 && ((new) & FPSCR_ENABLES_MASK) != 0) \
+ (void) __fe_nomask_env_priv (); \
+ } while (0)
+
/* The sticky bits in the FPSCR indicating exceptions have occurred. */
#define FPSCR_STICKY_BITS ((FE_ALL_EXCEPT | FE_ALL_INVALID) & ~FE_INVALID)
#include <fenv_libc.h>
#include <fpu_control.h>
-/* Mask for the exception enable bits. */
-#define _FPU_ALL_TRAPS (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM \
- | _FPU_MASK_XM | _FPU_MASK_IM)
-
-/* Mask the rounding mode bits. */
-#define _FPU_MASK_RN 0xfffffffffffffffcLL
-
-/* Mask everything but the rounding modes and non-IEEE arithmetic flags. */
-#define _FPU_MASK_NOT_RN_NI 0xffffffff00000807LL
-
-/* Mask restore rounding mode and exception enabled. */
-#define _FPU_MASK_TRAPS_RN 0xffffffffffffff00LL
-
-/* Mask FP result flags, preserve fraction rounded/inexact bits. */
-#define _FPU_MASK_FRAC_INEX_RET_CC 0xfffffffffff80fffLL
-
static __always_inline void
-__libc_feholdbits_ppc (fenv_t *envp, unsigned long long mask,
- unsigned long long bits)
+libc_feholdexcept_setround_ppc (fenv_t *envp, int r)
{
fenv_union_t old, new;
old.fenv = *envp = fegetenv_register ();
- new.l = (old.l & mask) | bits;
-
- /* If the old env had any enabled exceptions, then mask SIGFPE in the
- MSR FE0/FE1 bits. This may allow the FPU to run faster because it
- always takes the default action and can not generate SIGFPE. */
- if ((old.l & _FPU_ALL_TRAPS) != 0)
- (void) __fe_mask_env ();
+ __TEST_AND_ENTER_NON_STOP (old.l, 0ULL);
+ /* Clear everything and set the rounding mode. */
+ new.l = r;
fesetenv_register (new.fenv);
}
-static __always_inline void
-libc_feholdexcept_ppc (fenv_t *envp)
-{
- __libc_feholdbits_ppc (envp, _FPU_MASK_NOT_RN_NI, 0LL);
-}
-
-static __always_inline void
-libc_feholdexcept_setround_ppc (fenv_t *envp, int r)
-{
- __libc_feholdbits_ppc (envp, _FPU_MASK_NOT_RN_NI & _FPU_MASK_RN, r);
-}
-
-static __always_inline void
-libc_fesetround_ppc (int r)
-{
- __fesetround_inline (r);
-}
-
-static __always_inline int
-libc_fetestexcept_ppc (int e)
-{
- fenv_union_t u;
- u.fenv = fegetenv_register ();
- return u.l & e;
-}
-
-static __always_inline void
-libc_feholdsetround_ppc (fenv_t *e, int r)
-{
- __libc_feholdbits_ppc (e, _FPU_MASK_TRAPS_RN, r);
-}
-
static __always_inline unsigned long long
__libc_femergeenv_ppc (const fenv_t *envp, unsigned long long old_mask,
unsigned long long new_mask)
/* Merge bits while masking unwanted bits from new and old env. */
new.l = (old.l & old_mask) | (new.l & new_mask);
- /* If the old env has no enabled exceptions and the new env has any enabled
- exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the
- hardware into "precise mode" and may cause the FPU to run slower on some
- hardware. */
- if ((old.l & _FPU_ALL_TRAPS) == 0 && (new.l & _FPU_ALL_TRAPS) != 0)
- (void) __fe_nomask_env_priv ();
-
- /* If the old env had any enabled exceptions and the new env has no enabled
- exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
- FPU to run faster because it always takes the default action and can not
- generate SIGFPE. */
- if ((old.l & _FPU_ALL_TRAPS) != 0 && (new.l & _FPU_ALL_TRAPS) == 0)
- (void) __fe_mask_env ();
+ __TEST_AND_EXIT_NON_STOP (old.l, new.l);
+ __TEST_AND_ENTER_NON_STOP (old.l, new.l);
/* Atomically enable and raise (if appropriate) exceptions set in `new'. */
fesetenv_register (new.fenv);
static __always_inline int
libc_feupdateenv_test_ppc (fenv_t *envp, int ex)
{
- return __libc_femergeenv_ppc (envp, _FPU_MASK_TRAPS_RN,
- _FPU_MASK_FRAC_INEX_RET_CC) & ex;
+ return __libc_femergeenv_ppc (envp, ~FPSCR_CONTROL_MASK,
+ ~FPSCR_STATUS_MASK) & ex;
}
static __always_inline void
ctx->env = old.fenv;
if (__glibc_unlikely (new.l != old.l))
{
- if ((old.l & _FPU_ALL_TRAPS) != 0)
- (void) __fe_mask_env ();
+ __TEST_AND_ENTER_NON_STOP (old.l, 0ULL);
fesetenv_register (new.fenv);
ctx->updated_status = true;
}
new.fenv = *envp;
old.fenv = fegetenv_status ();
- /* If the old env has no enabled exceptions and the new env has any enabled
- exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the
- hardware into "precise mode" and may cause the FPU to run slower on some
- hardware. */
- if ((old.l & FPSCR_ENABLES_MASK) == 0 && (new.l & FPSCR_ENABLES_MASK) != 0)
- (void) __fe_nomask_env_priv ();
-
- /* If the old env had any enabled exceptions and the new env has no enabled
- exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
- FPU to run faster because it always takes the default action and can not
- generate SIGFPE. */
- if ((old.l & FPSCR_ENABLES_MASK) != 0 && (new.l & FPSCR_ENABLES_MASK) == 0)
- (void)__fe_mask_env ();
+ __TEST_AND_EXIT_NON_STOP (old.l, new.l);
+ __TEST_AND_ENTER_NON_STOP (old.l, new.l);
fesetenv_register (new.fenv);
if (old.l == new.l)
return 0;
- if ((old.l & FPSCR_ENABLES_MASK) == 0 && (new.l & FPSCR_ENABLES_MASK) != 0)
- (void) __fe_nomask_env_priv ();
-
- if ((old.l & FPSCR_ENABLES_MASK) != 0 && (new.l & FPSCR_ENABLES_MASK) == 0)
- (void) __fe_mask_env ();
+ __TEST_AND_EXIT_NON_STOP (old.l, new.l);
+ __TEST_AND_ENTER_NON_STOP (old.l, new.l);
fesetenv_mode (new.fenv);
return 0;
#include <fenv_libc.h>
#include <fpu_control.h>
-#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM)
-
int
__feupdateenv (const fenv_t *envp)
{
unchanged. */
new.l = (old.l & 0xffffffff1fffff00LL) | (new.l & 0x1ff80fff);
- /* If the old env has no enabled exceptions and the new env has any enabled
- exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put
- the hardware into "precise mode" and may cause the FPU to run slower on
- some hardware. */
- if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0)
- (void) __fe_nomask_env_priv ();
-
- /* If the old env had any enabled exceptions and the new env has no enabled
- exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
- FPU to run faster because it always takes the default action and can not
- generate SIGFPE. */
- if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0)
- (void)__fe_mask_env ();
+ __TEST_AND_EXIT_NON_STOP (old.l, new.l);
+ __TEST_AND_ENTER_NON_STOP (old.l, new.l);
/* Atomically enable and raise (if appropriate) exceptions set in `new'. */
fesetenv_register (new.fenv);
projects / thirdparty / glibc.git / commitdiff
