ls-ecaps: Add XT and TEE-Limited support reporting

PCIe r6.1 added TDISP with TEE Limited bits.
PCIe r7.0 added XT mode for IDE TLPs.

Define new bits and update the test.

Signed-off-by: Alexey Kardashevskiy <aik@amd.com>

diff --git a/lib/header.h b/lib/header.h
index 26cdf874d76a169c14080ad525581dd46997b4b0..61803869399d8d35643f36ca6e724d53ad6a2327 100644 (file)
--- a/lib/header.h
+++ b/lib/header.h
@@ -1540,17 +1540,20 @@
 #define  PCI_IDE_CAP_AGGREGATION_SUPP  0x10    /* Aggregation Supported */
 #define  PCI_IDE_CAP_PCRC_SUPP         0x20    /* PCRC Supported */
 #define  PCI_IDE_CAP_IDE_KM_SUPP       0x40    /* IDE_KM Protocol Supported */
+#define  PCI_IDE_CAP_SEL_CFG_SUPP      0x80    /* Selective IDE for Config Request Support */
 #define  PCI_IDE_CAP_ALG(x)    (((x) >> 8) & 0x1f) /* Supported Algorithms */
 #define  PCI_IDE_CAP_ALG_AES_GCM_256   0       /* AES-GCM 256 key size, 96b MAC */
 #define  PCI_IDE_CAP_LINK_TC_NUM(x)            (((x) >> 13) & 0x7) /* Number of TCs Supported for Link IDE */
 #define  PCI_IDE_CAP_SELECTIVE_STREAMS_NUM(x)  (((x) >> 16) & 0xff) /* Number of Selective IDE Streams Supported */
 #define  PCI_IDE_CAP_TEE_LIMITED_SUPP   0x1000000 /* TEE-Limited Stream Supported */
+#define  PCI_IDE_CAP_XT_SUPP           0x2000000 /* XT Supported */
 #define PCI_IDE_CTL            0x8
 #define  PCI_IDE_CTL_FLOWTHROUGH_IDE   0x4     /* Flow-Through IDE Stream Enabled */
 #define PCI_IDE_LINK_STREAM            0xC
 /* Link IDE Stream block, up to PCI_IDE_CAP_LINK_TC_NUM */
 /* Link IDE Stream Control Register */
 #define  PCI_IDE_LINK_CTL_EN           0x1     /* Link IDE Stream Enable */
+#define  PCI_IDE_LINK_CTL_XT           0x2     /* Link IDE Stream XT Enable */
 #define  PCI_IDE_LINK_CTL_TX_AGGR_NPR(x)(((x) >> 2) & 0x3) /* Tx Aggregation Mode NPR */
 #define  PCI_IDE_LINK_CTL_TX_AGGR_PR(x)        (((x) >> 4) & 0x3) /* Tx Aggregation Mode PR */
 #define  PCI_IDE_LINK_CTL_TX_AGGR_CPL(x)(((x) >> 6) & 0x3) /* Tx Aggregation Mode CPL */
@@ -1567,6 +1570,7 @@
 #define  PCI_IDE_SEL_CAP_BLOCKS_NUM(x) ((x) & 0xf) /* Number of Address Association Register Blocks */
 /* Selective IDE Stream Control Register */
 #define  PCI_IDE_SEL_CTL_EN            0x1     /* Selective IDE Stream Enable */
+#define  PCI_IDE_SEL_CTL_XT            0x2     /* Selective IDE Stream XT Enable */
 #define  PCI_IDE_SEL_CTL_TX_AGGR_NPR(x)        (((x) >> 2) & 0x3) /* Tx Aggregation Mode NPR */
 #define  PCI_IDE_SEL_CTL_TX_AGGR_PR(x) (((x) >> 4) & 0x3) /* Tx Aggregation Mode PR */
 #define  PCI_IDE_SEL_CTL_TX_AGGR_CPL(x)        (((x) >> 6) & 0x3) /* Tx Aggregation Mode CPL */
@@ -1576,6 +1580,7 @@
 #define  PCI_IDE_SEL_CTL_ALG(x)                (((x) >> 14) & 0x1f) /* Selected Algorithm */
 #define  PCI_IDE_SEL_CTL_TC(x)         (((x) >> 19) & 0x7)  /* Traffic Class */
 #define  PCI_IDE_SEL_CTL_DEFAULT       0x400000 /* Default Stream */
+#define  PCI_IDE_SEL_CTL_TEE_LIMITED   0x800000 /* TEE-Limited Stream */
 #define  PCI_IDE_SEL_CTL_ID(x)         (((x) >> 24) & 0xff) /* Stream ID */
 /* Selective IDE Stream Status Register */
 #define  PCI_IDE_SEL_STS_STATUS(x)     ((x) & 0xf) /* Selective IDE Stream State */

diff --git a/ls-ecaps.c b/ls-ecaps.c
index 1169daa7b6bb27e69169a84d2a39a38ed63997cb..a2c1313a22cf563954fc84987df33c3f7d22e878 100644 (file)
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -1665,7 +1665,7 @@ cap_ide(struct device *d, int where)
     if (l & PCI_IDE_CAP_SELECTIVE_IDE_SUPP)
         selnum = PCI_IDE_CAP_SELECTIVE_STREAMS_NUM(l) + 1;
 
-    printf("\t\tIDECap: Lnk=%d Sel=%d FlowThru%c PartHdr%c Aggr%c PCPC%c IDE_KM%c Alg='%s' TCs=%d TeeLim%c\n",
+    printf("\t\tIDECap: Lnk=%d Sel=%d FlowThru%c PartHdr%c Aggr%c PCPC%c IDE_KM%c SelCfg%c Alg='%s' TCs=%d TeeLim%c XT%c\n",
       linknum,
       selnum,
       FLAG(l, PCI_IDE_CAP_FLOWTHROUGH_IDE_SUPP),
@@ -1673,9 +1673,11 @@ cap_ide(struct device *d, int where)
       FLAG(l, PCI_IDE_CAP_AGGREGATION_SUPP),
       FLAG(l, PCI_IDE_CAP_PCRC_SUPP),
       FLAG(l, PCI_IDE_CAP_IDE_KM_SUPP),
+      FLAG(l, PCI_IDE_CAP_SEL_CFG_SUPP),
       ide_alg(buf2, sizeof(buf2), PCI_IDE_CAP_ALG(l)),
       PCI_IDE_CAP_LINK_TC_NUM(l) + 1,
-      FLAG(l, PCI_IDE_CAP_TEE_LIMITED_SUPP)
+      FLAG(l, PCI_IDE_CAP_TEE_LIMITED_SUPP),
+      FLAG(l, PCI_IDE_CAP_XT_SUPP)
       );
 
     l = get_conf_long(d, where + PCI_IDE_CTL);
@@ -1697,10 +1699,11 @@ cap_ide(struct device *d, int where)
           {
             // Link IDE Stream Control Register
             l = get_conf_long(d, off);
-            printf("\t\t%sLinkIDE#%d Ctl: En%c NPR%s PR%s CPL%s PCRC%c HdrEnc=%s Alg='%s' TC%d ID%d\n",
+            printf("\t\t%sLinkIDE#%d Ctl: En%c XT%c NPR%s PR%s CPL%s PCRC%c HdrEnc=%s Alg='%s' TC%d ID%d\n",
               offstr(offs, off),
               i,
               FLAG(l, PCI_IDE_LINK_CTL_EN),
+              FLAG(l, PCI_IDE_LINK_CTL_XT),
               aggr[PCI_IDE_LINK_CTL_TX_AGGR_NPR(l)],
               aggr[PCI_IDE_LINK_CTL_TX_AGGR_PR(l)],
               aggr[PCI_IDE_LINK_CTL_TX_AGGR_CPL(l)],
@@ -1744,10 +1747,11 @@ cap_ide(struct device *d, int where)
         // Selective IDE Stream Control Register
         l = get_conf_long(d, off);
 
-        printf("\t\t%sSelectiveIDE#%d Ctl: En%c NPR%s PR%s CPL%s PCRC%c CFG%c HdrEnc=%s Alg='%s' TC%d ID%d%s\n",
+        printf("\t\t%sSelectiveIDE#%d Ctl: En%c XT%c NPR%s PR%s CPL%s PCRC%c CFG%c HdrEnc=%s Alg='%s' TC%d TeeLim%c ID%d%s\n",
           offstr(offs, off),
           i,
           FLAG(l, PCI_IDE_SEL_CTL_EN),
+          FLAG(l, PCI_IDE_SEL_CTL_XT),
           aggr[PCI_IDE_SEL_CTL_TX_AGGR_NPR(l)],
           aggr[PCI_IDE_SEL_CTL_TX_AGGR_PR(l)],
           aggr[PCI_IDE_SEL_CTL_TX_AGGR_CPL(l)],
@@ -1756,6 +1760,7 @@ cap_ide(struct device *d, int where)
           TABLE(hdr_enc_mode, PCI_IDE_SEL_CTL_PART_ENC(l), buf1),
           ide_alg(buf2, sizeof(buf2), PCI_IDE_SEL_CTL_ALG(l)),
           PCI_IDE_SEL_CTL_TC(l),
+          FLAG(l, PCI_IDE_SEL_CTL_TEE_LIMITED),
           PCI_IDE_SEL_CTL_ID(l),
           (l & PCI_IDE_SEL_CTL_DEFAULT) ? " Default" : ""
           );

diff --git a/tests/cap-ide b/tests/cap-ide
index edae551ed56bb2ebbfca01ca0d0b14a3f2b73132..eabf5eac7da382adab477f859767b51f7fc70dd3 100644 (file)
--- a/tests/cap-ide
+++ b/tests/cap-ide
@@ -76,10 +76,10 @@ e1:00.0 Class 0800: Device aaaa:bbbb
                PASIDCap: Exec+ Priv+, Max PASID Width: 10
                PASIDCtl: Enable+ Exec- Priv-
        Capabilities: [830 v1] Integrity & Data Encryption
-               IDECap: Lnk=0 Sel=1 FlowThru- PartHdr- Aggr- PCPC- IDE_KM+ Alg='AES-GCM-256-96b' TCs=8 TeeLim+
+               IDECap: Lnk=0 Sel=1 FlowThru- PartHdr- Aggr- PCPC- IDE_KM+ SelCfg- Alg='AES-GCM-256-96b' TCs=8 TeeLim+ XT-
                IDECtl: FTEn-
                SelectiveIDE#0 Cap: RID#=1
-               SelectiveIDE#0 Ctl: En+ NPR- PR- CPL- PCRC- CFG- HdrEnc=no Alg='AES-GCM-256-96b' TC0 ID0 Default
+               SelectiveIDE#0 Ctl: En- XT- NPR- PR- CPL- PCRC- CFG- HdrEnc=no Alg='AES-GCM-256-96b' TC0 TeeLim- ID0
                SelectiveIDE#0 Sta: secure RecvChkFail-
                SelectiveIDE#0 RID: Valid+ Base=0 Limit=ffff SegBase=0
                SelectiveIDE#0 RID#0: Valid+ Base=0 Limit=ffffffffffffffff