phy: lynx-28g: restructure protocol configuration register accesses

Eliminate the need to calculate a lane_offset manually, and generate
some macros which access the protocol converter corresponding to the
correct lane in the PCC* registers.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Link: https://patch.msgid.link/20251125114847.804961-10-vladimir.oltean@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index def91c64a6ac5c90a9e55b552a3dfc1df677cd7d..5692ed8fc65f4cdea64dc731ed415ec316f34a6d 100644 (file)
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -12,17 +12,32 @@
 #define LYNX_28G_NUM_LANE                      8
 #define LYNX_28G_NUM_PLL                       2
 
+#define LNa_PCC_OFFSET(lane)                   (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
+
 /* General registers per SerDes block */
 #define PCC8                                   0x10a0
-#define PCC8_SGMII                             0x1
-#define PCC8_SGMII_DIS                         0x0
+#define PCC8_SGMIInCFG(lane, x)                        (((x) & GENMASK(2, 0)) << LNa_PCC_OFFSET(lane))
+#define PCC8_SGMIInCFG_EN(lane)                        PCC8_SGMIInCFG(lane, 1)
+#define PCC8_SGMIInCFG_MSK(lane)               PCC8_SGMIInCFG(lane, GENMASK(2, 0))
+#define PCC8_SGMIIn_KX(lane, x)                        ((((x) << 3) & BIT(3)) << LNa_PCC_OFFSET(lane))
+#define PCC8_SGMIIn_KX_MSK(lane)               PCC8_SGMIIn_KX(lane, 1)
+#define PCC8_MSK(lane)                         PCC8_SGMIInCFG_MSK(lane) | \
+                                               PCC8_SGMIIn_KX_MSK(lane)
 
 #define PCCC                                   0x10b0
-#define PCCC_10GBASER                          0x9
-#define PCCC_USXGMII                           0x1
-#define PCCC_SXGMII_DIS                                0x0
-
-#define LNa_PCC_OFFSET(lane)                   (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
+#define PCCC_SXGMIInCFG(lane, x)               (((x) & GENMASK(2, 0)) << LNa_PCC_OFFSET(lane))
+#define PCCC_SXGMIInCFG_EN(lane)               PCCC_SXGMIInCFG(lane, 1)
+#define PCCC_SXGMIInCFG_MSK(lane)              PCCC_SXGMIInCFG(lane, GENMASK(2, 0))
+#define PCCC_SXGMIInCFG_XFI(lane, x)           ((((x) << 3) & BIT(3)) << LNa_PCC_OFFSET(lane))
+#define PCCC_SXGMIInCFG_XFI_MSK(lane)          PCCC_SXGMIInCFG_XFI(lane, 1)
+#define PCCC_MSK(lane)                         PCCC_SXGMIInCFG_MSK(lane) | \
+                                               PCCC_SXGMIInCFG_XFI_MSK(lane)
+
+#define PCCD                                   0x10b4
+#define PCCD_E25GnCFG(lane, x)                 (((x) & GENMASK(2, 0)) << LNa_PCCD_OFFSET(lane))
+#define PCCD_E25GnCFG_EN(lane)                 PCCD_E25GnCFG(lane, 1)
+#define PCCD_E25GnCFG_MSK(lane)                        PCCD_E25GnCFG(lane, GENMASK(2, 0))
+#define PCCD_MSK(lane)                         PCCD_E25GnCFG_MSK(lane)
 
 /* Per PLL registers */
 #define PLLnRSTCTL(pll)                                (0x400 + (pll) * 0x100 + 0x0)
@@ -314,20 +329,21 @@ static void lynx_28g_lane_set_pll(struct lynx_28g_lane *lane,
 static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane)
 {
        struct lynx_28g_priv *priv = lane->priv;
-       u32 lane_offset = LNa_PCC_OFFSET(lane);
 
        /* Cleanup the protocol configuration registers of the current protocol */
        switch (lane->interface) {
        case PHY_INTERFACE_MODE_10GBASER:
-               lynx_28g_rmw(priv, PCCC,
-                            PCCC_SXGMII_DIS << lane_offset,
-                            GENMASK(3, 0) << lane_offset);
+               /* Cleanup the protocol configuration registers */
+               lynx_28g_rmw(priv, PCCC, 0, PCCC_MSK(lane));
                break;
        case PHY_INTERFACE_MODE_SGMII:
        case PHY_INTERFACE_MODE_1000BASEX:
-               lynx_28g_rmw(priv, PCC8,
-                            PCC8_SGMII_DIS << lane_offset,
-                            GENMASK(3, 0) << lane_offset);
+               /* Cleanup the protocol configuration registers */
+               lynx_28g_rmw(priv, PCC8, 0, PCC8_MSK(lane));
+
+               /* Disable the SGMII PCS */
+               lynx_28g_lane_rmw(lane, SGMIIaCR1, 0, SGMIIaCR1_SGPCS_EN);
+
                break;
        default:
                break;
@@ -336,16 +352,13 @@ static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane)
 
 static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
 {
-       u32 lane_offset = LNa_PCC_OFFSET(lane);
        struct lynx_28g_priv *priv = lane->priv;
        struct lynx_28g_pll *pll;
 
        lynx_28g_cleanup_lane(lane);
 
        /* Setup the lane to run in SGMII */
-       lynx_28g_rmw(priv, PCC8,
-                    PCC8_SGMII << lane_offset,
-                    GENMASK(3, 0) << lane_offset);
+       lynx_28g_rmw(priv, PCC8, PCC8_SGMIInCFG_EN(lane), PCC8_MSK(lane));
 
        /* Setup the protocol select and SerDes parallel interface width */
        lynx_28g_lane_rmw(lane, LNaGCR0,
@@ -390,15 +403,13 @@ static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
 static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
 {
        struct lynx_28g_priv *priv = lane->priv;
-       u32 lane_offset = LNa_PCC_OFFSET(lane);
        struct lynx_28g_pll *pll;
 
        lynx_28g_cleanup_lane(lane);
 
        /* Enable the SXGMII lane */
-       lynx_28g_rmw(priv, PCCC,
-                    PCCC_10GBASER << lane_offset,
-                    GENMASK(3, 0) << lane_offset);
+       lynx_28g_rmw(priv, PCCC, PCCC_SXGMIInCFG_EN(lane) |
+                    PCCC_SXGMIInCFG_XFI(lane, 1), PCCC_MSK(lane));
 
        /* Setup the protocol select and SerDes parallel interface width */
        lynx_28g_lane_rmw(lane, LNaGCR0,