Rename some int<->fp conversion IROps for consistency. No functional change. n...

2018-Dec-27: some of int<->fp conversion operations have been renamed so as to
have a trailing _DEP, meaning "deprecated".  This is because they don't
specify a rounding mode to be used for the conversion and so are
underspecified.  Their use should be replaced with equivalents that do specify
a rounding mode, either as a first argument or using a suffix on the name,
that indicates the rounding mode to use.

diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c
index d858c85e0bcca21da5f96d052d85e402a46dcffb..ff426be1520b89839c42e41accca4c88cbd4cbe8 100644 (file)
--- a/VEX/priv/guest_arm_toIR.c
+++ b/VEX/priv/guest_arm_toIR.c
@@ -7534,7 +7534,7 @@ Bool dis_neon_data_2reg_misc ( UInt theInstr, IRTemp condT )
                if (mreg & 1)
                   return False;
                mreg >>= 1;
-               putDRegI64(dreg, unop(Iop_F32toF16x4, getQReg(mreg)),
+               putDRegI64(dreg, unop(Iop_F32toF16x4_DEP, getQReg(mreg)),
                                 condT);
                DIP("vcvt.f16.f32 d%u, q%u\n", dreg, mreg);
             }
@@ -7589,22 +7589,22 @@ Bool dis_neon_data_2reg_misc ( UInt theInstr, IRTemp condT )
                return False;
             switch ((B >> 1) & 3) {
                case 0:
-                  op = Q ? Iop_I32StoFx4 : Iop_I32StoFx2;
+                  op = Q ? Iop_I32StoF32x4_DEP : Iop_I32StoF32x2_DEP;
                   DIP("vcvt.f32.s32 %c%u, %c%u\n",
                       Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
                   break;
                case 1:
-                  op = Q ? Iop_I32UtoFx4 : Iop_I32UtoFx2;
+                  op = Q ? Iop_I32UtoF32x4_DEP : Iop_I32UtoF32x2_DEP;
                   DIP("vcvt.f32.u32 %c%u, %c%u\n",
                       Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
                   break;
                case 2:
-                  op = Q ? Iop_FtoI32Sx4_RZ : Iop_FtoI32Sx2_RZ;
+                  op = Q ? Iop_F32toI32Sx4_RZ : Iop_F32toI32Sx2_RZ;
                   DIP("vcvt.s32.f32 %c%u, %c%u\n",
                       Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
                   break;
                case 3:
-                  op = Q ? Iop_FtoI32Ux4_RZ : Iop_FtoI32Ux2_RZ;
+                  op = Q ? Iop_F32toI32Ux4_RZ : Iop_F32toI32Ux2_RZ;
                   DIP("vcvt.u32.f32 %c%u, %c%u\n",
                       Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
                   break;

diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c
index 8421126473ff2077f30528820aa0ab7ca6b2736b..f8ef88fe63526b4b35572e1e208983bf07cabd9b 100644 (file)
--- a/VEX/priv/guest_mips_toIR.c
+++ b/VEX/priv/guest_mips_toIR.c
@@ -21639,10 +21639,10 @@ static Int msa_3R_1B(UInt cins, UChar wd, UChar ws) { /* 3R (0x1B) */
                      t1 = newTemp(Ity_I64);
                      t2 = newTemp(Ity_I64);
                      assign(t1,
-                            unop(Iop_F32toF16x4,
+                            unop(Iop_F32toF16x4_DEP,
                                  getWReg(ws)));
                      assign(t2,
-                            unop(Iop_F32toF16x4,
+                            unop(Iop_F32toF16x4_DEP,
                                  getWReg(wt)));
                      putWReg(wd,
                              binop(Iop_64HLtoV128,
@@ -24761,7 +24761,7 @@ static Int msa_2RF(UInt cins, UChar wd, UChar ws) { /* 2RF */
                case 0x00: { /* FTRUNC_S.W */
                      DIP("FTRUNC_S.W w%d, w%d", wd, ws);
                      calculateMSACSR(ws, wd, FTRUNCSW, 1);
-                     putWReg(wd, unop(Iop_FtoI32Sx4_RZ, getWReg(ws)));
+                     putWReg(wd, unop(Iop_F32toI32Sx4_RZ, getWReg(ws)));
                      break;
                   }
 
@@ -24808,7 +24808,7 @@ static Int msa_2RF(UInt cins, UChar wd, UChar ws) { /* 2RF */
                case 0x00: {  /* FTRUNC_U.W */
                      DIP("FTRUNC_U.W w%d, w%d", wd, ws);
                      calculateMSACSR(ws, wd, FTRUNCUW, 1);
-                     putWReg(wd, unop(Iop_FtoI32Ux4_RZ, getWReg(ws)));
+                     putWReg(wd, unop(Iop_F32toI32Ux4_RZ, getWReg(ws)));
                      break;
                   }
 
@@ -25515,7 +25515,7 @@ static Int msa_2RF(UInt cins, UChar wd, UChar ws) { /* 2RF */
                                                mkexpr(t3))),
                                    binop(Iop_AndV128,
                                          unop(Iop_NotV128, mkexpr(t4)),
-                                         unop(Iop_FtoI32Ux4_RZ,
+                                         unop(Iop_F32toI32Ux4_RZ,
                                               getWReg(ws)))));
                      break;
                   }
@@ -25621,7 +25621,7 @@ static Int msa_2RF(UInt cins, UChar wd, UChar ws) { /* 2RF */
                case 0x00: { /* FFINT_U.W */
                      DIP("FFINT_U.W w%d, w%d", wd, ws);
                      calculateMSACSR(ws, wt, FFINT_UW, 1);
-                     putWReg(wd, unop(Iop_I32UtoFx4, getWReg(ws)));
+                     putWReg(wd, unop(Iop_I32UtoF32x4_DEP, getWReg(ws)));
                      break;
                   }
 

diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index d685383be13f9cdad6e0c5f51a92333513159f31..c2d28f2f119d68452bc631d151807af9224178bb 100644 (file)
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -16087,7 +16087,7 @@ dis_vx_conv ( UInt theInstr, UInt opc2 )
          IRTemp hi64 = newTemp(Ity_I64);
          IRTemp lo64 = newTemp(Ity_I64);
          Bool un_signed = (opc2 == 0x110);
-         IROp op = un_signed ? Iop_QFtoI32Ux4_RZ : Iop_QFtoI32Sx4_RZ;
+         IROp op = un_signed ? Iop_QF32toI32Ux4_RZ : Iop_QF32toI32Sx4_RZ;
 
          DIP("xvcvsp%sxws v%u,v%u\n", un_signed ? "u" : "s", XT, XB);
          /* The xvcvsp{s|u}xws instruction is similar to vct{s|u}xs, except if src is a NaN,
@@ -16379,11 +16379,11 @@ dis_vx_conv ( UInt theInstr, UInt opc2 )
          break;
       case 0x170: // xvcvsxwsp (VSX Vector Convert Signed Integer Word to Single-Precision format)
          DIP("xvcvsxwsp v%u,v%u\n",  XT, XB);
-         putVSReg( XT, unop( Iop_I32StoFx4, getVSReg( XB ) ) );
+         putVSReg( XT, unop( Iop_I32StoF32x4_DEP, getVSReg( XB ) ) );
          break;
       case 0x150: // xvcvuxwsp (VSX Vector Convert Unsigned Integer Word to Single-Precision format)
          DIP("xvcvuxwsp v%u,v%u\n",  XT, XB);
-         putVSReg( XT, unop( Iop_I32UtoFx4, getVSReg( XB ) ) );
+         putVSReg( XT, unop( Iop_I32UtoF32x4_DEP, getVSReg( XB ) ) );
          break;
 
       default:
@@ -18846,7 +18846,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2,
              * V128 result.  The contents of the lower 64-bits is undefined.
              */
             DIP("xscvdphp v%d, v%d\n", (UInt)XT, (UInt)XB);
-            assign( result,  unop( Iop_F64toF16x2, mkexpr( vB ) ) );
+            assign( result,  unop( Iop_F64toF16x2_DEP, mkexpr( vB ) ) );
             assign( value, unop( Iop_64to32, unop( Iop_V128HIto64,
                                                    mkexpr( result ) ) ) );
             putVSReg( XT, mkexpr( result ) );
@@ -19629,7 +19629,7 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2,
             /* Iop_F32toF16x4 is V128 -> I64, scatter the 16-bit floats in the
              * I64 result to the V128 register to store.
              */
-            assign( tmp64, unop( Iop_F32toF16x4, mkexpr( vB ) ) );
+            assign( tmp64, unop( Iop_F32toF16x4_DEP, mkexpr( vB ) ) );
 
             /* Scatter 16-bit float values from returned 64-bit value
              * of V128 result.
@@ -27306,7 +27306,7 @@ static Bool dis_av_fp_convert ( UInt theInstr )
    case 0x30A: // vcfux (Convert from Unsigned Fixed-Point W, AV p156)
       DIP("vcfux v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
       putVReg( vD_addr, triop(Iop_Mul32Fx4, mkU32(Irrm_NEAREST),
-                              unop(Iop_I32UtoFx4, mkexpr(vB)),
+                              unop(Iop_I32UtoF32x4_DEP, mkexpr(vB)),
                               mkexpr(vInvScale)) );
       return True;
 
@@ -27314,14 +27314,14 @@ static Bool dis_av_fp_convert ( UInt theInstr )
       DIP("vcfsx v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
 
       putVReg( vD_addr, triop(Iop_Mul32Fx4, mkU32(Irrm_NEAREST),
-                              unop(Iop_I32StoFx4, mkexpr(vB)),
+                              unop(Iop_I32StoF32x4_DEP, mkexpr(vB)),
                               mkexpr(vInvScale)) );
       return True;
 
    case 0x38A: // vctuxs (Convert to Unsigned Fixed-Point W Saturate, AV p172)
       DIP("vctuxs v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
       putVReg( vD_addr,
-               unop(Iop_QFtoI32Ux4_RZ, 
+               unop(Iop_QF32toI32Ux4_RZ,
                     triop(Iop_Mul32Fx4, mkU32(Irrm_NEAREST),
                           mkexpr(vB), mkexpr(vScale))) );
       return True;
@@ -27329,7 +27329,7 @@ static Bool dis_av_fp_convert ( UInt theInstr )
    case 0x3CA: // vctsxs (Convert to Signed Fixed-Point W Saturate, AV p171)
       DIP("vctsxs v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
       putVReg( vD_addr, 
-               unop(Iop_QFtoI32Sx4_RZ, 
+               unop(Iop_QF32toI32Sx4_RZ,
                      triop(Iop_Mul32Fx4, mkU32(Irrm_NEAREST),
                            mkexpr(vB), mkexpr(vScale))) );
       return True;

diff --git a/VEX/priv/host_arm_isel.c b/VEX/priv/host_arm_isel.c
index 3db44f4952a3857f92d8a9c606439bde1680a8b2..da4f4aa8094c4c88612bf106ea742138f174fd40 100644 (file)
--- a/VEX/priv/host_arm_isel.c
+++ b/VEX/priv/host_arm_isel.c
@@ -3767,35 +3767,35 @@ static HReg iselNeon64Expr_wrk ( ISelEnv* env, const IRExpr* e )
                                           res, arg, size, False));
             return res;
          }
-         case Iop_FtoI32Sx2_RZ: {
+         case Iop_F32toI32Sx2_RZ: {
             HReg res = newVRegD(env);
             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
             addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoS,
                                           res, arg, 2, False));
             return res;
          }
-         case Iop_FtoI32Ux2_RZ: {
+         case Iop_F32toI32Ux2_RZ: {
             HReg res = newVRegD(env);
             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
             addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoU,
                                           res, arg, 2, False));
             return res;
          }
-         case Iop_I32StoFx2: {
+         case Iop_I32StoF32x2_DEP: {
             HReg res = newVRegD(env);
             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
             addInstr(env, ARMInstr_NUnary(ARMneon_VCVTStoF,
                                           res, arg, 2, False));
             return res;
          }
-         case Iop_I32UtoFx2: {
+         case Iop_I32UtoF32x2_DEP: {
             HReg res = newVRegD(env);
             HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
             addInstr(env, ARMInstr_NUnary(ARMneon_VCVTUtoF,
                                           res, arg, 2, False));
             return res;
          }
-         case Iop_F32toF16x4: {
+         case Iop_F32toF16x4_DEP: {
             HReg res = newVRegD(env);
             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
             addInstr(env, ARMInstr_NUnary(ARMneon_VCVTF32toF16,
@@ -4373,28 +4373,28 @@ static HReg iselNeonExpr_wrk ( ISelEnv* env, const IRExpr* e )
             addInstr(env, ARMInstr_NUnary(ARMneon_CLS, res, arg, size, True));
             return res;
          }
-         case Iop_FtoI32Sx4_RZ: {
+         case Iop_F32toI32Sx4_RZ: {
             HReg res = newVRegV(env);
             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
             addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoS,
                                           res, arg, 2, True));
             return res;
          }
-         case Iop_FtoI32Ux4_RZ: {
+         case Iop_F32toI32Ux4_RZ: {
             HReg res = newVRegV(env);
             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
             addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoU,
                                           res, arg, 2, True));
             return res;
          }
-         case Iop_I32StoFx4: {
+         case Iop_I32StoF32x4_DEP: {
             HReg res = newVRegV(env);
             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
             addInstr(env, ARMInstr_NUnary(ARMneon_VCVTStoF,
                                           res, arg, 2, True));
             return res;
          }
-         case Iop_I32UtoFx4: {
+         case Iop_I32UtoF32x4_DEP: {
             HReg res = newVRegV(env);
             HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
             addInstr(env, ARMInstr_NUnary(ARMneon_VCVTUtoF,

diff --git a/VEX/priv/host_mips_isel.c b/VEX/priv/host_mips_isel.c
index f1b65717519a6adf28ffc89c55afb21feb140df4..f6d5b0abeeb3ee10d1bcb340b298d899abf6c45b 100644 (file)
--- a/VEX/priv/host_mips_isel.c
+++ b/VEX/priv/host_mips_isel.c
@@ -2237,7 +2237,7 @@ static HReg iselWordExpr_R_wrk(ISelEnv * env, IRExpr * e)
             return reg;
          }
 
-         case Iop_F32toF16x4: {
+         case Iop_F32toF16x4_DEP: {
             vassert(mode64);
             vassert(has_msa);
             HReg v_arg = iselV128Expr(env, e->Iex.Unop.arg);
@@ -3056,7 +3056,7 @@ static HReg iselV128Expr_wrk(ISelEnv* env, IRExpr* e) {
                return v_dst;
             }
 
-         case Iop_I32UtoFx4: {
+         case Iop_I32UtoF32x4_DEP: {
                HReg v_src = iselV128Expr(env, e->Iex.Unop.arg);
                HReg v_dst = newVRegV(env);
                set_guest_MIPS_rounding_mode_MSA(env);
@@ -3066,7 +3066,7 @@ static HReg iselV128Expr_wrk(ISelEnv* env, IRExpr* e) {
                return v_dst;
             }
 
-         case Iop_FtoI32Sx4_RZ: {
+         case Iop_F32toI32Sx4_RZ: {
                HReg v_src = iselV128Expr(env, e->Iex.Unop.arg);
                HReg v_dst = newVRegV(env);
                addInstr(env,
@@ -3074,7 +3074,7 @@ static HReg iselV128Expr_wrk(ISelEnv* env, IRExpr* e) {
                return v_dst;
             }
 
-         case Iop_FtoI32Ux4_RZ: {
+         case Iop_F32toI32Ux4_RZ: {
                HReg v_src = iselV128Expr(env, e->Iex.Unop.arg);
                HReg v_dst = newVRegV(env);
                addInstr(env,
@@ -5819,7 +5819,7 @@ static void iselInt64Expr_wrk(HReg * rHi, HReg * rLo, ISelEnv * env, IRExpr * e)
             return;
          }
 
-         case Iop_F32toF16x4: {
+         case Iop_F32toF16x4_DEP: {
             vassert(has_msa);
             HReg v_arg = iselV128Expr(env, e->Iex.Unop.arg);
             HReg v_src = newVRegV(env);

diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c
index 4fc3eb54e75dd2348f05993e9e22c95ec5daded2..7254b5a40ac733379f02e42261ef8c650fb431fb 100644 (file)
--- a/VEX/priv/host_ppc_isel.c
+++ b/VEX/priv/host_ppc_isel.c
@@ -2518,7 +2518,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, const IRExpr* e,
          addInstr(env, mk_iMOVds_RR(r_dst, argregs[0]));
          return r_dst;
       }
-      case Iop_F32toF16x4: {
+      case Iop_F32toF16x4_DEP: {
          HReg vdst = newVRegV(env);    /* V128 */
          HReg dst  = newVRegI(env);    /* I64*/
          HReg r0 = newVRegI(env);    /* I16*/
@@ -5649,7 +5649,7 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, const IRExpr* e,
             return dst;
          }
 
-      case Iop_F64toF16x2:
+      case Iop_F64toF16x2_DEP:
          {
             HReg dst = newVRegV(env);
             HReg arg  = iselVecExpr(env, e->Iex.Unop.arg, IEndianess);
@@ -5697,7 +5697,7 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, const IRExpr* e,
             return dst;
          }
 
-      case Iop_F32toF16x4:
+      case Iop_F32toF16x4_DEP:
          {
             HReg dst = newVRegI(env);
             HReg tmp = newVRegV(env);
@@ -5781,10 +5781,10 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, const IRExpr* e,
 
       case Iop_RecipEst32Fx4: fpop = Pavfp_RCPF;    goto do_32Fx4_unary;
       case Iop_RSqrtEst32Fx4: fpop = Pavfp_RSQRTF;  goto do_32Fx4_unary;
-      case Iop_I32UtoFx4:     fpop = Pavfp_CVTU2F;  goto do_32Fx4_unary;
-      case Iop_I32StoFx4:     fpop = Pavfp_CVTS2F;  goto do_32Fx4_unary;
-      case Iop_QFtoI32Ux4_RZ: fpop = Pavfp_QCVTF2U; goto do_32Fx4_unary;
-      case Iop_QFtoI32Sx4_RZ: fpop = Pavfp_QCVTF2S; goto do_32Fx4_unary;
+      case Iop_I32UtoF32x4_DEP: fpop = Pavfp_CVTU2F;  goto do_32Fx4_unary;
+      case Iop_I32StoF32x4_DEP: fpop = Pavfp_CVTS2F;  goto do_32Fx4_unary;
+      case Iop_QF32toI32Ux4_RZ: fpop = Pavfp_QCVTF2U; goto do_32Fx4_unary;
+      case Iop_QF32toI32Sx4_RZ: fpop = Pavfp_QCVTF2S; goto do_32Fx4_unary;
       case Iop_RoundF32x4_RM: fpop = Pavfp_ROUNDM;  goto do_32Fx4_unary;
       case Iop_RoundF32x4_RP: fpop = Pavfp_ROUNDP;  goto do_32Fx4_unary;
       case Iop_RoundF32x4_RN: fpop = Pavfp_ROUNDN;  goto do_32Fx4_unary;

diff --git a/VEX/priv/ir_defs.c b/VEX/priv/ir_defs.c
index 93de80f913cce5e11912ad5be4b77946bc3a75a6..61b4a6dcff5e5c27610d3d9b2ea34b281cdf33ef 100644 (file)
--- a/VEX/priv/ir_defs.c
+++ b/VEX/priv/ir_defs.c
@@ -437,33 +437,33 @@ void ppIROp ( IROp op )
       case Iop_ReinterpF32asI32: vex_printf("ReinterpF32asI32"); return;
       case Iop_ReinterpI32asF32: vex_printf("ReinterpI32asF32"); return;
 
-      case Iop_I32UtoFx4: vex_printf("I32UtoFx4"); return;
-      case Iop_I32StoFx4: vex_printf("I32StoFx4"); return;
+      case Iop_I32UtoF32x4_DEP: vex_printf("I32UtoF32x4_DEP"); return;
+      case Iop_I32StoF32x4_DEP: vex_printf("I32StoF32x4_DEP"); return;
 
       case Iop_I32StoF32x4: vex_printf("I32StoF32x4"); return;
       case Iop_F32toI32Sx4: vex_printf("F32toI32Sx4"); return;
 
-      case Iop_F32toF16x4: vex_printf("F32toF16x4"); return;
+      case Iop_F32toF16x4_DEP: vex_printf("F32toF16x4_DEP"); return;
       case Iop_F16toF32x4: vex_printf("F16toF32x4"); return;
       case Iop_F16toF64x2: vex_printf("F16toF64x2"); return;
-      case Iop_F64toF16x2: vex_printf("F64toF16x2"); return;
+      case Iop_F64toF16x2_DEP: vex_printf("F64toF16x2_DEP"); return;
 
       case Iop_RSqrtEst32Fx4: vex_printf("RSqrtEst32Fx4"); return;
       case Iop_RSqrtEst32Ux4: vex_printf("RSqrtEst32Ux4"); return;
       case Iop_RSqrtEst32Fx2: vex_printf("RSqrtEst32Fx2"); return;
       case Iop_RSqrtEst32Ux2: vex_printf("RSqrtEst32Ux2"); return;
 
-      case Iop_QFtoI32Ux4_RZ: vex_printf("QFtoI32Ux4_RZ"); return;
-      case Iop_QFtoI32Sx4_RZ: vex_printf("QFtoI32Sx4_RZ"); return;
+      case Iop_QF32toI32Ux4_RZ: vex_printf("QF32toI32Ux4_RZ"); return;
+      case Iop_QF32toI32Sx4_RZ: vex_printf("QF32toI32Sx4_RZ"); return;
 
-      case Iop_FtoI32Ux4_RZ: vex_printf("FtoI32Ux4_RZ"); return;
-      case Iop_FtoI32Sx4_RZ: vex_printf("FtoI32Sx4_RZ"); return;
+      case Iop_F32toI32Ux4_RZ: vex_printf("F32toI32Ux4_RZ"); return;
+      case Iop_F32toI32Sx4_RZ: vex_printf("F32toI32Sx4_RZ"); return;
 
-      case Iop_I32UtoFx2: vex_printf("I32UtoFx2"); return;
-      case Iop_I32StoFx2: vex_printf("I32StoFx2"); return;
+      case Iop_I32UtoF32x2_DEP: vex_printf("I32UtoF32x2_DEP"); return;
+      case Iop_I32StoF32x2_DEP: vex_printf("I32StoF32x2_DEP"); return;
 
-      case Iop_FtoI32Ux2_RZ: vex_printf("FtoI32Ux2_RZ"); return;
-      case Iop_FtoI32Sx2_RZ: vex_printf("FtoI32Sx2_RZ"); return;
+      case Iop_F32toI32Ux2_RZ: vex_printf("F32toI32Ux2_RZ"); return;
+      case Iop_F32toI32Sx2_RZ: vex_printf("F32toI32Sx2_RZ"); return;
 
       case Iop_RoundF32x4_RM: vex_printf("RoundF32x4_RM"); return;
       case Iop_RoundF32x4_RP: vex_printf("RoundF32x4_RP"); return;
@@ -2749,8 +2749,8 @@ void typeOfPrimop ( IROp op,
       case Iop_Reverse32sIn64_x1:
       case Iop_Reverse8sIn32_x2: case Iop_Reverse16sIn32_x2:
       case Iop_Reverse8sIn16_x4:
-      case Iop_FtoI32Sx2_RZ: case Iop_FtoI32Ux2_RZ:
-      case Iop_I32StoFx2: case Iop_I32UtoFx2:
+      case Iop_F32toI32Sx2_RZ: case Iop_F32toI32Ux2_RZ:
+      case Iop_I32StoF32x2_DEP: case Iop_I32UtoF32x2_DEP:
       case Iop_RecipEst32Ux2: case Iop_RecipEst32Fx2:
       case Iop_Abs32Fx2:
       case Iop_RSqrtEst32Fx2:
@@ -2978,12 +2978,12 @@ void typeOfPrimop ( IROp op,
       case Iop_TruncF64asF32:
          UNARY(Ity_F64, Ity_F32);
 
-      case Iop_I32UtoFx4:
-      case Iop_I32StoFx4:
-      case Iop_QFtoI32Ux4_RZ:
-      case Iop_QFtoI32Sx4_RZ:
-      case Iop_FtoI32Ux4_RZ:
-      case Iop_FtoI32Sx4_RZ:
+      case Iop_I32UtoF32x4_DEP:
+      case Iop_I32StoF32x4_DEP:
+      case Iop_QF32toI32Ux4_RZ:
+      case Iop_QF32toI32Sx4_RZ:
+      case Iop_F32toI32Ux4_RZ:
+      case Iop_F32toI32Sx4_RZ:
       case Iop_RoundF32x4_RM:
       case Iop_RoundF32x4_RP:
       case Iop_RoundF32x4_RN:
@@ -3022,7 +3022,7 @@ void typeOfPrimop ( IROp op,
       case Iop_QNarrowUn16Sto8Ux8:
       case Iop_QNarrowUn32Sto16Ux4:
       case Iop_QNarrowUn64Sto32Ux2:
-      case Iop_F32toF16x4:
+      case Iop_F32toF16x4_DEP:
          UNARY(Ity_V128, Ity_I64);
 
       case Iop_Widen8Uto16x8:
@@ -3197,7 +3197,7 @@ void typeOfPrimop ( IROp op,
       case Iop_ZeroHI64ofV128:  case Iop_ZeroHI96ofV128:
       case Iop_ZeroHI112ofV128: case Iop_ZeroHI120ofV128:
       case Iop_F16toF64x2:
-      case Iop_F64toF16x2:
+      case Iop_F64toF16x2_DEP:
       case Iop_MulI128by10:
       case Iop_MulI128by10Carry:
       case Iop_Ctz8x16: case Iop_Ctz16x8:

diff --git a/VEX/pub/libvex_ir.h b/VEX/pub/libvex_ir.h
index f8ba2c7cd50e6587a037ce3f21e2b7cfbfca9b31..849b12455d2c7228266616188d20550cab150946 100644 (file)
--- a/VEX/pub/libvex_ir.h
+++ b/VEX/pub/libvex_ir.h
@@ -411,6 +411,13 @@ extern void ppIRTemp ( IRTemp );
    their functionality.  Such obscure ones are thus not directly visible
    in the IR, but their effects on guest state (memory and registers) 
    are made visible via the annotations in IRDirty structures.
+
+   2018-Dec-27: some of int<->fp conversion operations have been renamed so as
+   to have a trailing _DEP, meaning "deprecated".  This is because they don't
+   specify a rounding mode to be used for the conversion and so are
+   underspecified.  Their use should be replaced with equivalents that do
+   specify a rounding mode, either as a first argument or using a suffix on the
+   name, that indicates the rounding mode to use.
 */
 typedef
    enum { 
@@ -845,9 +852,12 @@ typedef
 
       /* ------------------ 64-bit SIMD FP ------------------------ */
 
-      /* Convertion to/from int */
-      Iop_I32UtoFx2,  Iop_I32StoFx2,    /* I32x4 -> F32x4 */
-      Iop_FtoI32Ux2_RZ,  Iop_FtoI32Sx2_RZ,    /* F32x4 -> I32x4 */
+      /* Conversion to/from int */
+      // Deprecated: these don't specify a rounding mode
+      Iop_I32UtoF32x2_DEP,  Iop_I32StoF32x2_DEP,    /* I32x2 -> F32x2 */
+
+      Iop_F32toI32Ux2_RZ,  Iop_F32toI32Sx2_RZ,    /* F32x2 -> I32x2 */
+
       /* Fixed32 format is floating-point number with fixed number of fraction
          bits. The number of fraction bits is passed as a second argument of
          type I8. */
@@ -1388,14 +1398,14 @@ typedef
          rounding mode argument. Instead the irop trailers _R{M,P,N,Z}
          indicate the mode: {-inf, +inf, nearest, zero} respectively. */
 
-      // FIXME These carry no rounding mode
-      Iop_I32UtoFx4,     Iop_I32StoFx4,       /* I32x4 -> F32x4       */
+      // These carry no rounding mode and are therefore deprecated
+      Iop_I32UtoF32x4_DEP, Iop_I32StoF32x4_DEP,  /* I32x4 -> F32x4 */
 
       Iop_I32StoF32x4, /* IRRoundingMode(I32) x V128 -> V128 */
       Iop_F32toI32Sx4, /* IRRoundingMode(I32) x V128 -> V128 */
 
-      Iop_FtoI32Ux4_RZ,  Iop_FtoI32Sx4_RZ,    /* F32x4 -> I32x4       */
-      Iop_QFtoI32Ux4_RZ, Iop_QFtoI32Sx4_RZ,   /* F32x4 -> I32x4 (saturating) */
+      Iop_F32toI32Ux4_RZ,  Iop_F32toI32Sx4_RZ,  /* F32x4 -> I32x4       */
+      Iop_QF32toI32Ux4_RZ, Iop_QF32toI32Sx4_RZ, /* F32x4 -> I32x4 (saturating) */
       Iop_RoundF32x4_RM, Iop_RoundF32x4_RP,   /* round to fp integer  */
       Iop_RoundF32x4_RN, Iop_RoundF32x4_RZ,   /* round to fp integer  */
       /* Fixed32 format is floating-point number with fixed number of fraction
@@ -1407,10 +1417,11 @@ typedef
       /* --- Single to/from half conversion --- */
       /* FIXME: what kind of rounding in F32x4 -> F16x4 case? */
       // FIXME these carry no rounding mode
-      Iop_F32toF16x4, Iop_F16toF32x4,         /* F32x4 <-> F16x4      */
+      Iop_F32toF16x4_DEP,     /* F32x4 -> F16x4, NO ROUNDING MODE */
+      Iop_F16toF32x4,         /* F16x4 -> F32x4 */
 
       /* -- Double to/from half conversion -- */
-      Iop_F64toF16x2, // FIXME this carries no rounding mode (?)
+      Iop_F64toF16x2_DEP, // F64x2 -> F16x2, NO ROUNDING MODE
       Iop_F16toF64x2,
 
       /* Values from two registers converted in smaller type and put in one
@@ -1606,6 +1617,7 @@ typedef
             [Foo16(a,b), Foo16(c,d), Foo16(e,f), Foo16(g,h)] */
       Iop_PwAdd8x16, Iop_PwAdd16x8, Iop_PwAdd32x4,
       Iop_PwAdd32Fx2,
+
       /* Longening variant is unary. The resulting vector contains two times
          less elements than operand, but they are two times wider.
          Example:

diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c
index c6ac3a5f1a46dfd503cf7471fc95a364222b3d0c..4706f277d982ba93c41b754f230ed4c8e40ca419 100644 (file)
--- a/memcheck/mc_translate.c
+++ b/memcheck/mc_translate.c
@@ -2912,7 +2912,7 @@ IROp vanillaNarrowingOpOfShape ( IROp qnarrowOp )
       case Iop_QNarrowUn32Uto16Ux4:
       case Iop_QNarrowUn32Sto16Sx4:
       case Iop_QNarrowUn32Sto16Ux4:
-      case Iop_F32toF16x4:
+      case Iop_F32toF16x4_DEP:
          return Iop_NarrowUn32to16x4;
       case Iop_QNarrowUn16Uto8Ux8:
       case Iop_QNarrowUn16Sto8Sx8:
@@ -2984,7 +2984,7 @@ IRAtom* vectorNarrowUnV128 ( MCEnv* mce, IROp narrow_op,
       case Iop_NarrowUn16to8x8:
       case Iop_NarrowUn32to16x4:
       case Iop_NarrowUn64to32x2:
-      case Iop_F32toF16x4:
+      case Iop_F32toF16x4_DEP:
          at1 = assignNew('V', mce, Ity_I64, unop(narrow_op, vatom1));
          return at1;
       default:
@@ -4871,10 +4871,10 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
          return unary64Fx4(mce, vatom);
 
       case Iop_RecipEst32Fx4:
-      case Iop_I32UtoFx4:
-      case Iop_I32StoFx4:
-      case Iop_QFtoI32Ux4_RZ:
-      case Iop_QFtoI32Sx4_RZ:
+      case Iop_I32UtoF32x4_DEP:
+      case Iop_I32StoF32x4_DEP:
+      case Iop_QF32toI32Ux4_RZ:
+      case Iop_QF32toI32Sx4_RZ:
       case Iop_RoundF32x4_RM:
       case Iop_RoundF32x4_RP:
       case Iop_RoundF32x4_RN:
@@ -4886,8 +4886,8 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
       case Iop_Log2_32Fx4:
          return unary32Fx4(mce, vatom);
 
-      case Iop_I32UtoFx2:
-      case Iop_I32StoFx2:
+      case Iop_I32UtoF32x2_DEP:
+      case Iop_I32StoF32x2_DEP:
       case Iop_RecipEst32Fx2:
       case Iop_RecipEst32Ux2:
       case Iop_Abs32Fx2:
@@ -4940,7 +4940,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
       case Iop_MulI128by10:
       case Iop_MulI128by10Carry:
       case Iop_F16toF64x2:
-      case Iop_F64toF16x2:
+      case Iop_F64toF16x2_DEP:
          // FIXME JRS 2018-Nov-15.  This is surely not correct!
          return vatom;
 
@@ -5117,16 +5117,16 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
       case Iop_CmpNEZ32x2:
       case Iop_Clz32x2:
       case Iop_Cls32x2:
-      case Iop_FtoI32Ux2_RZ:
-      case Iop_FtoI32Sx2_RZ:
+      case Iop_F32toI32Ux2_RZ:
+      case Iop_F32toI32Sx2_RZ:
       case Iop_Abs32x2:
          return mkPCast32x2(mce, vatom);
 
       case Iop_CmpNEZ32x4:
       case Iop_Clz32x4:
       case Iop_Cls32x4:
-      case Iop_FtoI32Ux4_RZ:
-      case Iop_FtoI32Sx4_RZ:
+      case Iop_F32toI32Ux4_RZ:
+      case Iop_F32toI32Sx4_RZ:
       case Iop_Abs32x4:
       case Iop_RSqrtEst32Ux4:
       case Iop_Ctz32x4:
@@ -5161,7 +5161,7 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
       case Iop_QNarrowUn64Sto32Sx2:
       case Iop_QNarrowUn64Sto32Ux2:
       case Iop_QNarrowUn64Uto32Ux2:
-      case Iop_F32toF16x4:
+      case Iop_F32toF16x4_DEP:
          return vectorNarrowUnV128(mce, op, vatom);
 
       case Iop_Widen8Sto16x8:

diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c
index 1047fa354cfe8b8f2111ae182191cd4f3929952e..97d953fb559e3bf0efb8458364e1f67a79d60878 100644 (file)
--- a/memcheck/tests/vbit-test/irops.c
+++ b/memcheck/tests/vbit-test/irops.c
@@ -344,10 +344,10 @@ static irop_t irops[] = {
   { DEFOP(Iop_CmpNEZ8x4, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Reverse8sIn32_x1, UNDEF_UNKNOWN) },
   /* ------------------ 64-bit SIMD FP ------------------------ */
-  { DEFOP(Iop_I32UtoFx2, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_I32StoFx2, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_FtoI32Ux2_RZ, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_FtoI32Sx2_RZ, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_I32UtoF32x2_DEP, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_I32StoF32x2_DEP, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_F32toI32Ux2_RZ, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_F32toI32Sx2_RZ, UNDEF_UNKNOWN), },
   { DEFOP(Iop_F32ToFixed32Ux2_RZ, UNDEF_UNKNOWN), },
   { DEFOP(Iop_F32ToFixed32Sx2_RZ, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Fixed32UToF32x2_RN, UNDEF_UNKNOWN), },
@@ -638,14 +638,14 @@ static irop_t irops[] = {
   { DEFOP(Iop_RecipStep32Fx4, UNDEF_UNKNOWN), },
   { DEFOP(Iop_RSqrtEst32Fx4, UNDEF_UNKNOWN), },
   { DEFOP(Iop_RSqrtStep32Fx4, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_I32UtoFx4, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_I32StoFx4, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_I32UtoF32x4_DEP, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_I32StoF32x4_DEP, UNDEF_UNKNOWN), },
   { DEFOP(Iop_I32StoF32x4, UNDEF_UNKNOWN), },
   { DEFOP(Iop_F32toI32Sx4, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_FtoI32Ux4_RZ, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_FtoI32Sx4_RZ, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_QFtoI32Ux4_RZ, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_QFtoI32Sx4_RZ, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_F32toI32Ux4_RZ, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_F32toI32Sx4_RZ, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_QF32toI32Ux4_RZ, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_QF32toI32Sx4_RZ, UNDEF_UNKNOWN), },
   { DEFOP(Iop_RoundF32x4_RM, UNDEF_UNKNOWN), },
   { DEFOP(Iop_RoundF32x4_RP, UNDEF_UNKNOWN), },
   { DEFOP(Iop_RoundF32x4_RN, UNDEF_UNKNOWN), },
@@ -654,9 +654,9 @@ static irop_t irops[] = {
   { DEFOP(Iop_F32ToFixed32Sx4_RZ, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Fixed32UToF32x4_RN, UNDEF_UNKNOWN), },
   { DEFOP(Iop_Fixed32SToF32x4_RN, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_F32toF16x4, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_F32toF16x4_DEP, UNDEF_UNKNOWN), },
   { DEFOP(Iop_F16toF32x4, UNDEF_UNKNOWN), },
-  { DEFOP(Iop_F64toF16x2, UNDEF_UNKNOWN), },
+  { DEFOP(Iop_F64toF16x2_DEP, UNDEF_UNKNOWN), },
   { DEFOP(Iop_F16toF64x2, UNDEF_UNKNOWN), },
   { DEFOP(Iop_F32x4_2toQ16x8, UNDEF_UNKNOWN), },
   { DEFOP(Iop_F64x2_2toQ32x4, UNDEF_UNKNOWN), },