--- /dev/null
+#as: -menable-sysreg-checking -I$srcdir/$subdir -march=armv8-a+poe2
+#as: -I$srcdir/$subdir -march=armv8-a
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: d5183600 msr afgdtp0_el1, x0
+.*: d5383600 mrs x0, afgdtp0_el1
+.*: d5183620 msr afgdtp1_el1, x0
+.*: d5383620 mrs x0, afgdtp1_el1
+.*: d5183640 msr afgdtp2_el1, x0
+.*: d5383640 mrs x0, afgdtp2_el1
+.*: d5183660 msr afgdtp3_el1, x0
+.*: d5383660 mrs x0, afgdtp3_el1
+.*: d5183680 msr afgdtp4_el1, x0
+.*: d5383680 mrs x0, afgdtp4_el1
+.*: d51836a0 msr afgdtp5_el1, x0
+.*: d53836a0 mrs x0, afgdtp5_el1
+.*: d51836c0 msr afgdtp6_el1, x0
+.*: d53836c0 mrs x0, afgdtp6_el1
+.*: d51836e0 msr afgdtp7_el1, x0
+.*: d53836e0 mrs x0, afgdtp7_el1
+.*: d5183700 msr afgdtp8_el1, x0
+.*: d5383700 mrs x0, afgdtp8_el1
+.*: d5183720 msr afgdtp9_el1, x0
+.*: d5383720 mrs x0, afgdtp9_el1
+.*: d5183740 msr afgdtp10_el1, x0
+.*: d5383740 mrs x0, afgdtp10_el1
+.*: d5183760 msr afgdtp11_el1, x0
+.*: d5383760 mrs x0, afgdtp11_el1
+.*: d5183780 msr afgdtp12_el1, x0
+.*: d5383780 mrs x0, afgdtp12_el1
+.*: d51837a0 msr afgdtp13_el1, x0
+.*: d53837a0 mrs x0, afgdtp13_el1
+.*: d51837c0 msr afgdtp14_el1, x0
+.*: d53837c0 mrs x0, afgdtp14_el1
+.*: d51837e0 msr afgdtp15_el1, x0
+.*: d53837e0 mrs x0, afgdtp15_el1
+.*: d51d3600 msr afgdtp0_el12, x0
+.*: d53d3600 mrs x0, afgdtp0_el12
+.*: d51d3620 msr afgdtp1_el12, x0
+.*: d53d3620 mrs x0, afgdtp1_el12
+.*: d51d3640 msr afgdtp2_el12, x0
+.*: d53d3640 mrs x0, afgdtp2_el12
+.*: d51d3660 msr afgdtp3_el12, x0
+.*: d53d3660 mrs x0, afgdtp3_el12
+.*: d51d3680 msr afgdtp4_el12, x0
+.*: d53d3680 mrs x0, afgdtp4_el12
+.*: d51d36a0 msr afgdtp5_el12, x0
+.*: d53d36a0 mrs x0, afgdtp5_el12
+.*: d51d36c0 msr afgdtp6_el12, x0
+.*: d53d36c0 mrs x0, afgdtp6_el12
+.*: d51d36e0 msr afgdtp7_el12, x0
+.*: d53d36e0 mrs x0, afgdtp7_el12
+.*: d51d3700 msr afgdtp8_el12, x0
+.*: d53d3700 mrs x0, afgdtp8_el12
+.*: d51d3720 msr afgdtp9_el12, x0
+.*: d53d3720 mrs x0, afgdtp9_el12
+.*: d51d3740 msr afgdtp10_el12, x0
+.*: d53d3740 mrs x0, afgdtp10_el12
+.*: d51d3760 msr afgdtp11_el12, x0
+.*: d53d3760 mrs x0, afgdtp11_el12
+.*: d51d3780 msr afgdtp12_el12, x0
+.*: d53d3780 mrs x0, afgdtp12_el12
+.*: d51d37a0 msr afgdtp13_el12, x0
+.*: d53d37a0 mrs x0, afgdtp13_el12
+.*: d51d37c0 msr afgdtp14_el12, x0
+.*: d53d37c0 mrs x0, afgdtp14_el12
+.*: d51d37e0 msr afgdtp15_el12, x0
+.*: d53d37e0 mrs x0, afgdtp15_el12
+.*: d51c3600 msr afgdtp0_el2, x0
+.*: d53c3600 mrs x0, afgdtp0_el2
+.*: d51c3620 msr afgdtp1_el2, x0
+.*: d53c3620 mrs x0, afgdtp1_el2
+.*: d51c3640 msr afgdtp2_el2, x0
+.*: d53c3640 mrs x0, afgdtp2_el2
+.*: d51c3660 msr afgdtp3_el2, x0
+.*: d53c3660 mrs x0, afgdtp3_el2
+.*: d51c3680 msr afgdtp4_el2, x0
+.*: d53c3680 mrs x0, afgdtp4_el2
+.*: d51c36a0 msr afgdtp5_el2, x0
+.*: d53c36a0 mrs x0, afgdtp5_el2
+.*: d51c36c0 msr afgdtp6_el2, x0
+.*: d53c36c0 mrs x0, afgdtp6_el2
+.*: d51c36e0 msr afgdtp7_el2, x0
+.*: d53c36e0 mrs x0, afgdtp7_el2
+.*: d51c3700 msr afgdtp8_el2, x0
+.*: d53c3700 mrs x0, afgdtp8_el2
+.*: d51c3720 msr afgdtp9_el2, x0
+.*: d53c3720 mrs x0, afgdtp9_el2
+.*: d51c3740 msr afgdtp10_el2, x0
+.*: d53c3740 mrs x0, afgdtp10_el2
+.*: d51c3760 msr afgdtp11_el2, x0
+.*: d53c3760 mrs x0, afgdtp11_el2
+.*: d51c3780 msr afgdtp12_el2, x0
+.*: d53c3780 mrs x0, afgdtp12_el2
+.*: d51c37a0 msr afgdtp13_el2, x0
+.*: d53c37a0 mrs x0, afgdtp13_el2
+.*: d51c37c0 msr afgdtp14_el2, x0
+.*: d53c37c0 mrs x0, afgdtp14_el2
+.*: d51c37e0 msr afgdtp15_el2, x0
+.*: d53c37e0 mrs x0, afgdtp15_el2
+.*: d51e3600 msr afgdtp0_el3, x0
+.*: d53e3600 mrs x0, afgdtp0_el3
+.*: d51e3620 msr afgdtp1_el3, x0
+.*: d53e3620 mrs x0, afgdtp1_el3
+.*: d51e3640 msr afgdtp2_el3, x0
+.*: d53e3640 mrs x0, afgdtp2_el3
+.*: d51e3660 msr afgdtp3_el3, x0
+.*: d53e3660 mrs x0, afgdtp3_el3
+.*: d51e3680 msr afgdtp4_el3, x0
+.*: d53e3680 mrs x0, afgdtp4_el3
+.*: d51e36a0 msr afgdtp5_el3, x0
+.*: d53e36a0 mrs x0, afgdtp5_el3
+.*: d51e36c0 msr afgdtp6_el3, x0
+.*: d53e36c0 mrs x0, afgdtp6_el3
+.*: d51e36e0 msr afgdtp7_el3, x0
+.*: d53e36e0 mrs x0, afgdtp7_el3
+.*: d51e3700 msr afgdtp8_el3, x0
+.*: d53e3700 mrs x0, afgdtp8_el3
+.*: d51e3720 msr afgdtp9_el3, x0
+.*: d53e3720 mrs x0, afgdtp9_el3
+.*: d51e3740 msr afgdtp10_el3, x0
+.*: d53e3740 mrs x0, afgdtp10_el3
+.*: d51e3760 msr afgdtp11_el3, x0
+.*: d53e3760 mrs x0, afgdtp11_el3
+.*: d51e3780 msr afgdtp12_el3, x0
+.*: d53e3780 mrs x0, afgdtp12_el3
+.*: d51e37a0 msr afgdtp13_el3, x0
+.*: d53e37a0 mrs x0, afgdtp13_el3
+.*: d51e37c0 msr afgdtp14_el3, x0
+.*: d53e37c0 mrs x0, afgdtp14_el3
+.*: d51e37e0 msr afgdtp15_el3, x0
+.*: d53e37e0 mrs x0, afgdtp15_el3
+.*: d5183800 msr afgdtu0_el1, x0
+.*: d5383800 mrs x0, afgdtu0_el1
+.*: d5183820 msr afgdtu1_el1, x0
+.*: d5383820 mrs x0, afgdtu1_el1
+.*: d5183840 msr afgdtu2_el1, x0
+.*: d5383840 mrs x0, afgdtu2_el1
+.*: d5183860 msr afgdtu3_el1, x0
+.*: d5383860 mrs x0, afgdtu3_el1
+.*: d5183880 msr afgdtu4_el1, x0
+.*: d5383880 mrs x0, afgdtu4_el1
+.*: d51838a0 msr afgdtu5_el1, x0
+.*: d53838a0 mrs x0, afgdtu5_el1
+.*: d51838c0 msr afgdtu6_el1, x0
+.*: d53838c0 mrs x0, afgdtu6_el1
+.*: d51838e0 msr afgdtu7_el1, x0
+.*: d53838e0 mrs x0, afgdtu7_el1
+.*: d5183900 msr afgdtu8_el1, x0
+.*: d5383900 mrs x0, afgdtu8_el1
+.*: d5183920 msr afgdtu9_el1, x0
+.*: d5383920 mrs x0, afgdtu9_el1
+.*: d5183940 msr afgdtu10_el1, x0
+.*: d5383940 mrs x0, afgdtu10_el1
+.*: d5183960 msr afgdtu11_el1, x0
+.*: d5383960 mrs x0, afgdtu11_el1
+.*: d5183980 msr afgdtu12_el1, x0
+.*: d5383980 mrs x0, afgdtu12_el1
+.*: d51839a0 msr afgdtu13_el1, x0
+.*: d53839a0 mrs x0, afgdtu13_el1
+.*: d51839c0 msr afgdtu14_el1, x0
+.*: d53839c0 mrs x0, afgdtu14_el1
+.*: d51839e0 msr afgdtu15_el1, x0
+.*: d53839e0 mrs x0, afgdtu15_el1
+.*: d51d3800 msr afgdtu0_el12, x0
+.*: d53d3800 mrs x0, afgdtu0_el12
+.*: d51d3820 msr afgdtu1_el12, x0
+.*: d53d3820 mrs x0, afgdtu1_el12
+.*: d51d3840 msr afgdtu2_el12, x0
+.*: d53d3840 mrs x0, afgdtu2_el12
+.*: d51d3860 msr afgdtu3_el12, x0
+.*: d53d3860 mrs x0, afgdtu3_el12
+.*: d51d3880 msr afgdtu4_el12, x0
+.*: d53d3880 mrs x0, afgdtu4_el12
+.*: d51d38a0 msr afgdtu5_el12, x0
+.*: d53d38a0 mrs x0, afgdtu5_el12
+.*: d51d38c0 msr afgdtu6_el12, x0
+.*: d53d38c0 mrs x0, afgdtu6_el12
+.*: d51d38e0 msr afgdtu7_el12, x0
+.*: d53d38e0 mrs x0, afgdtu7_el12
+.*: d51d3900 msr afgdtu8_el12, x0
+.*: d53d3900 mrs x0, afgdtu8_el12
+.*: d51d3920 msr afgdtu9_el12, x0
+.*: d53d3920 mrs x0, afgdtu9_el12
+.*: d51d3940 msr afgdtu10_el12, x0
+.*: d53d3940 mrs x0, afgdtu10_el12
+.*: d51d3960 msr afgdtu11_el12, x0
+.*: d53d3960 mrs x0, afgdtu11_el12
+.*: d51d3980 msr afgdtu12_el12, x0
+.*: d53d3980 mrs x0, afgdtu12_el12
+.*: d51d39a0 msr afgdtu13_el12, x0
+.*: d53d39a0 mrs x0, afgdtu13_el12
+.*: d51d39c0 msr afgdtu14_el12, x0
+.*: d53d39c0 mrs x0, afgdtu14_el12
+.*: d51d39e0 msr afgdtu15_el12, x0
+.*: d53d39e0 mrs x0, afgdtu15_el12
+.*: d51c3800 msr afgdtu0_el2, x0
+.*: d53c3800 mrs x0, afgdtu0_el2
+.*: d51c3820 msr afgdtu1_el2, x0
+.*: d53c3820 mrs x0, afgdtu1_el2
+.*: d51c3840 msr afgdtu2_el2, x0
+.*: d53c3840 mrs x0, afgdtu2_el2
+.*: d51c3860 msr afgdtu3_el2, x0
+.*: d53c3860 mrs x0, afgdtu3_el2
+.*: d51c3880 msr afgdtu4_el2, x0
+.*: d53c3880 mrs x0, afgdtu4_el2
+.*: d51c38a0 msr afgdtu5_el2, x0
+.*: d53c38a0 mrs x0, afgdtu5_el2
+.*: d51c38c0 msr afgdtu6_el2, x0
+.*: d53c38c0 mrs x0, afgdtu6_el2
+.*: d51c38e0 msr afgdtu7_el2, x0
+.*: d53c38e0 mrs x0, afgdtu7_el2
+.*: d51c3900 msr afgdtu8_el2, x0
+.*: d53c3900 mrs x0, afgdtu8_el2
+.*: d51c3920 msr afgdtu9_el2, x0
+.*: d53c3920 mrs x0, afgdtu9_el2
+.*: d51c3940 msr afgdtu10_el2, x0
+.*: d53c3940 mrs x0, afgdtu10_el2
+.*: d51c3960 msr afgdtu11_el2, x0
+.*: d53c3960 mrs x0, afgdtu11_el2
+.*: d51c3980 msr afgdtu12_el2, x0
+.*: d53c3980 mrs x0, afgdtu12_el2
+.*: d51c39a0 msr afgdtu13_el2, x0
+.*: d53c39a0 mrs x0, afgdtu13_el2
+.*: d51c39c0 msr afgdtu14_el2, x0
+.*: d53c39c0 mrs x0, afgdtu14_el2
+.*: d51c39e0 msr afgdtu15_el2, x0
+.*: d53c39e0 mrs x0, afgdtu15_el2
+.*: d5183200 msr fgdtp0_el1, x0
+.*: d5383200 mrs x0, fgdtp0_el1
+.*: d5183220 msr fgdtp1_el1, x0
+.*: d5383220 mrs x0, fgdtp1_el1
+.*: d5183240 msr fgdtp2_el1, x0
+.*: d5383240 mrs x0, fgdtp2_el1
+.*: d5183260 msr fgdtp3_el1, x0
+.*: d5383260 mrs x0, fgdtp3_el1
+.*: d5183280 msr fgdtp4_el1, x0
+.*: d5383280 mrs x0, fgdtp4_el1
+.*: d51832a0 msr fgdtp5_el1, x0
+.*: d53832a0 mrs x0, fgdtp5_el1
+.*: d51832c0 msr fgdtp6_el1, x0
+.*: d53832c0 mrs x0, fgdtp6_el1
+.*: d51832e0 msr fgdtp7_el1, x0
+.*: d53832e0 mrs x0, fgdtp7_el1
+.*: d5183300 msr fgdtp8_el1, x0
+.*: d5383300 mrs x0, fgdtp8_el1
+.*: d5183320 msr fgdtp9_el1, x0
+.*: d5383320 mrs x0, fgdtp9_el1
+.*: d5183340 msr fgdtp10_el1, x0
+.*: d5383340 mrs x0, fgdtp10_el1
+.*: d5183360 msr fgdtp11_el1, x0
+.*: d5383360 mrs x0, fgdtp11_el1
+.*: d5183380 msr fgdtp12_el1, x0
+.*: d5383380 mrs x0, fgdtp12_el1
+.*: d51833a0 msr fgdtp13_el1, x0
+.*: d53833a0 mrs x0, fgdtp13_el1
+.*: d51833c0 msr fgdtp14_el1, x0
+.*: d53833c0 mrs x0, fgdtp14_el1
+.*: d51833e0 msr fgdtp15_el1, x0
+.*: d53833e0 mrs x0, fgdtp15_el1
+.*: d51d3200 msr fgdtp0_el12, x0
+.*: d53d3200 mrs x0, fgdtp0_el12
+.*: d51d3220 msr fgdtp1_el12, x0
+.*: d53d3220 mrs x0, fgdtp1_el12
+.*: d51d3240 msr fgdtp2_el12, x0
+.*: d53d3240 mrs x0, fgdtp2_el12
+.*: d51d3260 msr fgdtp3_el12, x0
+.*: d53d3260 mrs x0, fgdtp3_el12
+.*: d51d3280 msr fgdtp4_el12, x0
+.*: d53d3280 mrs x0, fgdtp4_el12
+.*: d51d32a0 msr fgdtp5_el12, x0
+.*: d53d32a0 mrs x0, fgdtp5_el12
+.*: d51d32c0 msr fgdtp6_el12, x0
+.*: d53d32c0 mrs x0, fgdtp6_el12
+.*: d51d32e0 msr fgdtp7_el12, x0
+.*: d53d32e0 mrs x0, fgdtp7_el12
+.*: d51d3300 msr fgdtp8_el12, x0
+.*: d53d3300 mrs x0, fgdtp8_el12
+.*: d51d3320 msr fgdtp9_el12, x0
+.*: d53d3320 mrs x0, fgdtp9_el12
+.*: d51d3340 msr fgdtp10_el12, x0
+.*: d53d3340 mrs x0, fgdtp10_el12
+.*: d51d3360 msr fgdtp11_el12, x0
+.*: d53d3360 mrs x0, fgdtp11_el12
+.*: d51d3380 msr fgdtp12_el12, x0
+.*: d53d3380 mrs x0, fgdtp12_el12
+.*: d51d33a0 msr fgdtp13_el12, x0
+.*: d53d33a0 mrs x0, fgdtp13_el12
+.*: d51d33c0 msr fgdtp14_el12, x0
+.*: d53d33c0 mrs x0, fgdtp14_el12
+.*: d51d33e0 msr fgdtp15_el12, x0
+.*: d53d33e0 mrs x0, fgdtp15_el12
+.*: d51c3200 msr fgdtp0_el2, x0
+.*: d53c3200 mrs x0, fgdtp0_el2
+.*: d51c3220 msr fgdtp1_el2, x0
+.*: d53c3220 mrs x0, fgdtp1_el2
+.*: d51c3240 msr fgdtp2_el2, x0
+.*: d53c3240 mrs x0, fgdtp2_el2
+.*: d51c3260 msr fgdtp3_el2, x0
+.*: d53c3260 mrs x0, fgdtp3_el2
+.*: d51c3280 msr fgdtp4_el2, x0
+.*: d53c3280 mrs x0, fgdtp4_el2
+.*: d51c32a0 msr fgdtp5_el2, x0
+.*: d53c32a0 mrs x0, fgdtp5_el2
+.*: d51c32c0 msr fgdtp6_el2, x0
+.*: d53c32c0 mrs x0, fgdtp6_el2
+.*: d51c32e0 msr fgdtp7_el2, x0
+.*: d53c32e0 mrs x0, fgdtp7_el2
+.*: d51c3300 msr fgdtp8_el2, x0
+.*: d53c3300 mrs x0, fgdtp8_el2
+.*: d51c3320 msr fgdtp9_el2, x0
+.*: d53c3320 mrs x0, fgdtp9_el2
+.*: d51c3340 msr fgdtp10_el2, x0
+.*: d53c3340 mrs x0, fgdtp10_el2
+.*: d51c3360 msr fgdtp11_el2, x0
+.*: d53c3360 mrs x0, fgdtp11_el2
+.*: d51c3380 msr fgdtp12_el2, x0
+.*: d53c3380 mrs x0, fgdtp12_el2
+.*: d51c33a0 msr fgdtp13_el2, x0
+.*: d53c33a0 mrs x0, fgdtp13_el2
+.*: d51c33c0 msr fgdtp14_el2, x0
+.*: d53c33c0 mrs x0, fgdtp14_el2
+.*: d51c33e0 msr fgdtp15_el2, x0
+.*: d53c33e0 mrs x0, fgdtp15_el2
+.*: d51e3200 msr fgdtp0_el3, x0
+.*: d53e3200 mrs x0, fgdtp0_el3
+.*: d51e3220 msr fgdtp1_el3, x0
+.*: d53e3220 mrs x0, fgdtp1_el3
+.*: d51e3240 msr fgdtp2_el3, x0
+.*: d53e3240 mrs x0, fgdtp2_el3
+.*: d51e3260 msr fgdtp3_el3, x0
+.*: d53e3260 mrs x0, fgdtp3_el3
+.*: d51e3280 msr fgdtp4_el3, x0
+.*: d53e3280 mrs x0, fgdtp4_el3
+.*: d51e32a0 msr fgdtp5_el3, x0
+.*: d53e32a0 mrs x0, fgdtp5_el3
+.*: d51e32c0 msr fgdtp6_el3, x0
+.*: d53e32c0 mrs x0, fgdtp6_el3
+.*: d51e32e0 msr fgdtp7_el3, x0
+.*: d53e32e0 mrs x0, fgdtp7_el3
+.*: d51e3300 msr fgdtp8_el3, x0
+.*: d53e3300 mrs x0, fgdtp8_el3
+.*: d51e3320 msr fgdtp9_el3, x0
+.*: d53e3320 mrs x0, fgdtp9_el3
+.*: d51e3340 msr fgdtp10_el3, x0
+.*: d53e3340 mrs x0, fgdtp10_el3
+.*: d51e3360 msr fgdtp11_el3, x0
+.*: d53e3360 mrs x0, fgdtp11_el3
+.*: d51e3380 msr fgdtp12_el3, x0
+.*: d53e3380 mrs x0, fgdtp12_el3
+.*: d51e33a0 msr fgdtp13_el3, x0
+.*: d53e33a0 mrs x0, fgdtp13_el3
+.*: d51e33c0 msr fgdtp14_el3, x0
+.*: d53e33c0 mrs x0, fgdtp14_el3
+.*: d51e33e0 msr fgdtp15_el3, x0
+.*: d53e33e0 mrs x0, fgdtp15_el3
+.*: d5183400 msr fgdtu0_el1, x0
+.*: d5383400 mrs x0, fgdtu0_el1
+.*: d5183420 msr fgdtu1_el1, x0
+.*: d5383420 mrs x0, fgdtu1_el1
+.*: d5183440 msr fgdtu2_el1, x0
+.*: d5383440 mrs x0, fgdtu2_el1
+.*: d5183460 msr fgdtu3_el1, x0
+.*: d5383460 mrs x0, fgdtu3_el1
+.*: d5183480 msr fgdtu4_el1, x0
+.*: d5383480 mrs x0, fgdtu4_el1
+.*: d51834a0 msr fgdtu5_el1, x0
+.*: d53834a0 mrs x0, fgdtu5_el1
+.*: d51834c0 msr fgdtu6_el1, x0
+.*: d53834c0 mrs x0, fgdtu6_el1
+.*: d51834e0 msr fgdtu7_el1, x0
+.*: d53834e0 mrs x0, fgdtu7_el1
+.*: d5183500 msr fgdtu8_el1, x0
+.*: d5383500 mrs x0, fgdtu8_el1
+.*: d5183520 msr fgdtu9_el1, x0
+.*: d5383520 mrs x0, fgdtu9_el1
+.*: d5183540 msr fgdtu10_el1, x0
+.*: d5383540 mrs x0, fgdtu10_el1
+.*: d5183560 msr fgdtu11_el1, x0
+.*: d5383560 mrs x0, fgdtu11_el1
+.*: d5183580 msr fgdtu12_el1, x0
+.*: d5383580 mrs x0, fgdtu12_el1
+.*: d51835a0 msr fgdtu13_el1, x0
+.*: d53835a0 mrs x0, fgdtu13_el1
+.*: d51835c0 msr fgdtu14_el1, x0
+.*: d53835c0 mrs x0, fgdtu14_el1
+.*: d51835e0 msr fgdtu15_el1, x0
+.*: d53835e0 mrs x0, fgdtu15_el1
+.*: d51d3400 msr fgdtu0_el12, x0
+.*: d53d3400 mrs x0, fgdtu0_el12
+.*: d51d3420 msr fgdtu1_el12, x0
+.*: d53d3420 mrs x0, fgdtu1_el12
+.*: d51d3440 msr fgdtu2_el12, x0
+.*: d53d3440 mrs x0, fgdtu2_el12
+.*: d51d3460 msr fgdtu3_el12, x0
+.*: d53d3460 mrs x0, fgdtu3_el12
+.*: d51d3480 msr fgdtu4_el12, x0
+.*: d53d3480 mrs x0, fgdtu4_el12
+.*: d51d34a0 msr fgdtu5_el12, x0
+.*: d53d34a0 mrs x0, fgdtu5_el12
+.*: d51d34c0 msr fgdtu6_el12, x0
+.*: d53d34c0 mrs x0, fgdtu6_el12
+.*: d51d34e0 msr fgdtu7_el12, x0
+.*: d53d34e0 mrs x0, fgdtu7_el12
+.*: d51d3500 msr fgdtu8_el12, x0
+.*: d53d3500 mrs x0, fgdtu8_el12
+.*: d51d3520 msr fgdtu9_el12, x0
+.*: d53d3520 mrs x0, fgdtu9_el12
+.*: d51d3540 msr fgdtu10_el12, x0
+.*: d53d3540 mrs x0, fgdtu10_el12
+.*: d51d3560 msr fgdtu11_el12, x0
+.*: d53d3560 mrs x0, fgdtu11_el12
+.*: d51d3580 msr fgdtu12_el12, x0
+.*: d53d3580 mrs x0, fgdtu12_el12
+.*: d51d35a0 msr fgdtu13_el12, x0
+.*: d53d35a0 mrs x0, fgdtu13_el12
+.*: d51d35c0 msr fgdtu14_el12, x0
+.*: d53d35c0 mrs x0, fgdtu14_el12
+.*: d51d35e0 msr fgdtu15_el12, x0
+.*: d53d35e0 mrs x0, fgdtu15_el12
+.*: d51c3400 msr fgdtu0_el2, x0
+.*: d53c3400 mrs x0, fgdtu0_el2
+.*: d51c3420 msr fgdtu1_el2, x0
+.*: d53c3420 mrs x0, fgdtu1_el2
+.*: d51c3440 msr fgdtu2_el2, x0
+.*: d53c3440 mrs x0, fgdtu2_el2
+.*: d51c3460 msr fgdtu3_el2, x0
+.*: d53c3460 mrs x0, fgdtu3_el2
+.*: d51c3480 msr fgdtu4_el2, x0
+.*: d53c3480 mrs x0, fgdtu4_el2
+.*: d51c34a0 msr fgdtu5_el2, x0
+.*: d53c34a0 mrs x0, fgdtu5_el2
+.*: d51c34c0 msr fgdtu6_el2, x0
+.*: d53c34c0 mrs x0, fgdtu6_el2
+.*: d51c34e0 msr fgdtu7_el2, x0
+.*: d53c34e0 mrs x0, fgdtu7_el2
+.*: d51c3500 msr fgdtu8_el2, x0
+.*: d53c3500 mrs x0, fgdtu8_el2
+.*: d51c3520 msr fgdtu9_el2, x0
+.*: d53c3520 mrs x0, fgdtu9_el2
+.*: d51c3540 msr fgdtu10_el2, x0
+.*: d53c3540 mrs x0, fgdtu10_el2
+.*: d51c3560 msr fgdtu11_el2, x0
+.*: d53c3560 mrs x0, fgdtu11_el2
+.*: d51c3580 msr fgdtu12_el2, x0
+.*: d53c3580 mrs x0, fgdtu12_el2
+.*: d51c35a0 msr fgdtu13_el2, x0
+.*: d53c35a0 mrs x0, fgdtu13_el2
+.*: d51c35c0 msr fgdtu14_el2, x0
+.*: d53c35c0 mrs x0, fgdtu14_el2
+.*: d51c35e0 msr fgdtu15_el2, x0
+.*: d53c35e0 mrs x0, fgdtu15_el2
+.*: d51820c0 msr dpotbr0_el1, x0
+.*: d53820c0 mrs x0, dpotbr0_el1
+.*: d51820e0 msr dpotbr1_el1, x0
+.*: d53820e0 mrs x0, dpotbr1_el1
+.*: d51d20c0 msr dpotbr0_el12, x0
+.*: d53d20c0 mrs x0, dpotbr0_el12
+.*: d51d20e0 msr dpotbr1_el12, x0
+.*: d53d20e0 mrs x0, dpotbr1_el12
+.*: d51c20c0 msr dpotbr0_el2, x0
+.*: d53c20c0 mrs x0, dpotbr0_el2
+.*: d51c20e0 msr dpotbr1_el2, x0
+.*: d53c20e0 mrs x0, dpotbr1_el2
+.*: d51e20c0 msr dpotbr0_el3, x0
+.*: d53e20c0 mrs x0, dpotbr0_el3
+.*: d51bd000 msr tpidr3_el0, x0
+.*: d53bd000 mrs x0, tpidr3_el0
+.*: d518d000 msr tpidr3_el1, x0
+.*: d538d000 mrs x0, tpidr3_el1
+.*: d51dd000 msr tpidr3_el12, x0
+.*: d53dd000 mrs x0, tpidr3_el12
+.*: d51cd000 msr tpidr3_el2, x0
+.*: d53cd000 mrs x0, tpidr3_el2
+.*: d51ed000 msr tpidr3_el3, x0
+.*: d53ed000 mrs x0, tpidr3_el3
+.*: d5182080 msr irtbru_el1, x0
+.*: d5382080 mrs x0, irtbru_el1
+.*: d51d2080 msr irtbru_el12, x0
+.*: d53d2080 mrs x0, irtbru_el12
+.*: d51c2080 msr irtbru_el2, x0
+.*: d53c2080 mrs x0, irtbru_el2
+.*: d51820a0 msr irtbrp_el1, x0
+.*: d53820a0 mrs x0, irtbrp_el1
+.*: d51d20a0 msr irtbrp_el12, x0
+.*: d53d20a0 mrs x0, irtbrp_el12
+.*: d51c20a0 msr irtbrp_el2, x0
+.*: d53c20a0 mrs x0, irtbrp_el2
+.*: d51e20a0 msr irtbrp_el3, x0
+.*: d53e20a0 mrs x0, irtbrp_el3
+.*: d51821e0 msr ldstt_el1, x0
+.*: d53821e0 mrs x0, ldstt_el1
+.*: d51d21e0 msr ldstt_el12, x0
+.*: d53d21e0 mrs x0, ldstt_el12
+.*: d51c21e0 msr ldstt_el2, x0
+.*: d53c21e0 mrs x0, ldstt_el2
+.*: d5184040 msr stindex_el1, x0
+.*: d5384040 mrs x0, stindex_el1
+.*: d51d4040 msr stindex_el12, x0
+.*: d53d4040 mrs x0, stindex_el12
+.*: d51c4040 msr stindex_el2, x0
+.*: d53c4040 mrs x0, stindex_el2
+.*: d51e4040 msr stindex_el3, x0
+.*: d53e4040 mrs x0, stindex_el3
+.*: d51b4060 msr tindex_el0, x0
+.*: d53b4060 mrs x0, tindex_el0
+.*: d5184060 msr tindex_el1, x0
+.*: d5384060 mrs x0, tindex_el1
+.*: d51d4060 msr tindex_el12, x0
+.*: d53d4060 mrs x0, tindex_el12
+.*: d51c4060 msr tindex_el2, x0
+.*: d53c4060 mrs x0, tindex_el2
+.*: d51e4060 msr tindex_el3, x0
+.*: d53e4060 mrs x0, tindex_el3
+.*: d518a2c0 msr tttbru_el1, x0
+.*: d538a2c0 mrs x0, tttbru_el1
+.*: d51da2c0 msr tttbru_el12, x0
+.*: d53da2c0 mrs x0, tttbru_el12
+.*: d51ca2c0 msr tttbru_el2, x0
+.*: d53ca2c0 mrs x0, tttbru_el2
+.*: d518a2e0 msr tttbrp_el1, x0
+.*: d538a2e0 mrs x0, tttbrp_el1
+.*: d51da2e0 msr tttbrp_el12, x0
+.*: d53da2e0 mrs x0, tttbrp_el12
+.*: d51ca2e0 msr tttbrp_el2, x0
+.*: d53ca2e0 mrs x0, tttbrp_el2
+.*: d51ea2e0 msr tttbrp_el3, x0
+.*: d53ea2e0 mrs x0, tttbrp_el3
+.*: d51b4540 msr dpocr_el0, x0
+.*: d53b4540 mrs x0, dpocr_el0
+.*: d51c2220 msr vnccr_el2, x0
+.*: d53c2220 mrs x0, vnccr_el2
SYSREG ("actlrmask_el1", CPENC (3,0,1,4,1), 0, AARCH64_FEATURE (V9_5A)) /* SRMASK */
SYSREG ("actlrmask_el12", CPENC (3,5,1,4,1), 0, AARCH64_FEATURE (V9_5A)) /* SRMASK */
SYSREG ("actlrmask_el2", CPENC (3,4,1,4,1), 0, AARCH64_FEATURE (V9_5A)) /* SRMASK */
+ SYSREG ("afgdtp0_el1", CPENC (3,0,3,6,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp0_el12", CPENC (3,5,3,6,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp0_el2", CPENC (3,4,3,6,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp0_el3", CPENC (3,6,3,6,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp10_el1", CPENC (3,0,3,7,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp10_el12", CPENC (3,5,3,7,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp10_el2", CPENC (3,4,3,7,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp10_el3", CPENC (3,6,3,7,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp11_el1", CPENC (3,0,3,7,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp11_el12", CPENC (3,5,3,7,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp11_el2", CPENC (3,4,3,7,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp11_el3", CPENC (3,6,3,7,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp12_el1", CPENC (3,0,3,7,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp12_el12", CPENC (3,5,3,7,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp12_el2", CPENC (3,4,3,7,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp12_el3", CPENC (3,6,3,7,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp13_el1", CPENC (3,0,3,7,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp13_el12", CPENC (3,5,3,7,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp13_el2", CPENC (3,4,3,7,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp13_el3", CPENC (3,6,3,7,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp14_el1", CPENC (3,0,3,7,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp14_el12", CPENC (3,5,3,7,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp14_el2", CPENC (3,4,3,7,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp14_el3", CPENC (3,6,3,7,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp15_el1", CPENC (3,0,3,7,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp15_el12", CPENC (3,5,3,7,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp15_el2", CPENC (3,4,3,7,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp15_el3", CPENC (3,6,3,7,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp1_el1", CPENC (3,0,3,6,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp1_el12", CPENC (3,5,3,6,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp1_el2", CPENC (3,4,3,6,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp1_el3", CPENC (3,6,3,6,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp2_el1", CPENC (3,0,3,6,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp2_el12", CPENC (3,5,3,6,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp2_el2", CPENC (3,4,3,6,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp2_el3", CPENC (3,6,3,6,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp3_el1", CPENC (3,0,3,6,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp3_el12", CPENC (3,5,3,6,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp3_el2", CPENC (3,4,3,6,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp3_el3", CPENC (3,6,3,6,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp4_el1", CPENC (3,0,3,6,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp4_el12", CPENC (3,5,3,6,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp4_el2", CPENC (3,4,3,6,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp4_el3", CPENC (3,6,3,6,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp5_el1", CPENC (3,0,3,6,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp5_el12", CPENC (3,5,3,6,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp5_el2", CPENC (3,4,3,6,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp5_el3", CPENC (3,6,3,6,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp6_el1", CPENC (3,0,3,6,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp6_el12", CPENC (3,5,3,6,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp6_el2", CPENC (3,4,3,6,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp6_el3", CPENC (3,6,3,6,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp7_el1", CPENC (3,0,3,6,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp7_el12", CPENC (3,5,3,6,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp7_el2", CPENC (3,4,3,6,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp7_el3", CPENC (3,6,3,6,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp8_el1", CPENC (3,0,3,7,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp8_el12", CPENC (3,5,3,7,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp8_el2", CPENC (3,4,3,7,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp8_el3", CPENC (3,6,3,7,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp9_el1", CPENC (3,0,3,7,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp9_el12", CPENC (3,5,3,7,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp9_el2", CPENC (3,4,3,7,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtp9_el3", CPENC (3,6,3,7,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu0_el1", CPENC (3,0,3,8,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu0_el12", CPENC (3,5,3,8,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu0_el2", CPENC (3,4,3,8,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu10_el1", CPENC (3,0,3,9,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu10_el12", CPENC (3,5,3,9,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu10_el2", CPENC (3,4,3,9,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu11_el1", CPENC (3,0,3,9,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu11_el12", CPENC (3,5,3,9,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu11_el2", CPENC (3,4,3,9,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu12_el1", CPENC (3,0,3,9,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu12_el12", CPENC (3,5,3,9,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu12_el2", CPENC (3,4,3,9,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu13_el1", CPENC (3,0,3,9,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu13_el12", CPENC (3,5,3,9,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu13_el2", CPENC (3,4,3,9,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu14_el1", CPENC (3,0,3,9,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu14_el12", CPENC (3,5,3,9,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu14_el2", CPENC (3,4,3,9,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu15_el1", CPENC (3,0,3,9,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu15_el12", CPENC (3,5,3,9,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu15_el2", CPENC (3,4,3,9,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu1_el1", CPENC (3,0,3,8,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu1_el12", CPENC (3,5,3,8,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu1_el2", CPENC (3,4,3,8,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu2_el1", CPENC (3,0,3,8,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu2_el12", CPENC (3,5,3,8,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu2_el2", CPENC (3,4,3,8,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu3_el1", CPENC (3,0,3,8,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu3_el12", CPENC (3,5,3,8,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu3_el2", CPENC (3,4,3,8,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu4_el1", CPENC (3,0,3,8,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu4_el12", CPENC (3,5,3,8,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu4_el2", CPENC (3,4,3,8,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu5_el1", CPENC (3,0,3,8,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu5_el12", CPENC (3,5,3,8,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu5_el2", CPENC (3,4,3,8,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu6_el1", CPENC (3,0,3,8,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu6_el12", CPENC (3,5,3,8,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu6_el2", CPENC (3,4,3,8,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu7_el1", CPENC (3,0,3,8,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu7_el12", CPENC (3,5,3,8,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu7_el2", CPENC (3,4,3,8,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu8_el1", CPENC (3,0,3,9,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu8_el12", CPENC (3,5,3,9,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu8_el2", CPENC (3,4,3,9,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu9_el1", CPENC (3,0,3,9,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu9_el12", CPENC (3,5,3,9,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("afgdtu9_el2", CPENC (3,4,3,9,1), 0, AARCH64_FEATURE (POE2))
SYSREG ("afsr0_el1", CPENC (3,0,5,1,0), 0, AARCH64_NO_FEATURES)
SYSREG ("afsr0_el12", CPENC (3,5,5,1,0), 0, AARCH64_NO_FEATURES)
SYSREG ("afsr0_el2", CPENC (3,4,5,1,0), 0, AARCH64_NO_FEATURES)
SYSREG ("disr_el1", CPENC (3,0,12,1,1), 0, AARCH64_FEATURE (RAS))
SYSREG ("dit", CPENC (3,3,4,2,5), 0, AARCH64_FEATURE (V8_3A)) /* DIT */
SYSREG ("dlr_el0", CPENC (3,3,4,5,1), 0, AARCH64_NO_FEATURES)
+ SYSREG ("dpocr_el0", CPENC (3,3,4,5,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("dpotbr0_el1", CPENC (3,0,2,0,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("dpotbr0_el12", CPENC (3,5,2,0,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("dpotbr0_el2", CPENC (3,4,2,0,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("dpotbr0_el3", CPENC (3,6,2,0,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("dpotbr1_el1", CPENC (3,0,2,0,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("dpotbr1_el12", CPENC (3,5,2,0,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("dpotbr1_el2", CPENC (3,4,2,0,7), 0, AARCH64_FEATURE (POE2))
SYSREG ("dspsr_el0", CPENC (3,3,4,5,0), 0, AARCH64_NO_FEATURES)
SYSREG ("elr_el1", CPENC (3,0,4,0,1), 0, AARCH64_NO_FEATURES)
SYSREG ("elr_el12", CPENC (3,5,4,0,1), 0, AARCH64_NO_FEATURES)
SYSREG ("far_el12", CPENC (3,5,6,0,0), 0, AARCH64_NO_FEATURES)
SYSREG ("far_el2", CPENC (3,4,6,0,0), 0, AARCH64_NO_FEATURES)
SYSREG ("far_el3", CPENC (3,6,6,0,0), 0, AARCH64_NO_FEATURES)
+ SYSREG ("fgdtp0_el1", CPENC (3,0,3,2,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp0_el12", CPENC (3,5,3,2,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp0_el2", CPENC (3,4,3,2,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp0_el3", CPENC (3,6,3,2,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp10_el1", CPENC (3,0,3,3,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp10_el12", CPENC (3,5,3,3,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp10_el2", CPENC (3,4,3,3,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp10_el3", CPENC (3,6,3,3,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp11_el1", CPENC (3,0,3,3,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp11_el12", CPENC (3,5,3,3,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp11_el2", CPENC (3,4,3,3,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp11_el3", CPENC (3,6,3,3,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp12_el1", CPENC (3,0,3,3,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp12_el12", CPENC (3,5,3,3,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp12_el2", CPENC (3,4,3,3,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp12_el3", CPENC (3,6,3,3,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp13_el1", CPENC (3,0,3,3,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp13_el12", CPENC (3,5,3,3,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp13_el2", CPENC (3,4,3,3,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp13_el3", CPENC (3,6,3,3,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp14_el1", CPENC (3,0,3,3,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp14_el12", CPENC (3,5,3,3,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp14_el2", CPENC (3,4,3,3,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp14_el3", CPENC (3,6,3,3,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp15_el1", CPENC (3,0,3,3,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp15_el12", CPENC (3,5,3,3,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp15_el2", CPENC (3,4,3,3,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp15_el3", CPENC (3,6,3,3,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp1_el1", CPENC (3,0,3,2,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp1_el12", CPENC (3,5,3,2,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp1_el2", CPENC (3,4,3,2,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp1_el3", CPENC (3,6,3,2,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp2_el1", CPENC (3,0,3,2,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp2_el12", CPENC (3,5,3,2,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp2_el2", CPENC (3,4,3,2,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp2_el3", CPENC (3,6,3,2,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp3_el1", CPENC (3,0,3,2,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp3_el12", CPENC (3,5,3,2,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp3_el2", CPENC (3,4,3,2,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp3_el3", CPENC (3,6,3,2,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp4_el1", CPENC (3,0,3,2,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp4_el12", CPENC (3,5,3,2,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp4_el2", CPENC (3,4,3,2,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp4_el3", CPENC (3,6,3,2,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp5_el1", CPENC (3,0,3,2,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp5_el12", CPENC (3,5,3,2,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp5_el2", CPENC (3,4,3,2,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp5_el3", CPENC (3,6,3,2,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp6_el1", CPENC (3,0,3,2,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp6_el12", CPENC (3,5,3,2,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp6_el2", CPENC (3,4,3,2,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp6_el3", CPENC (3,6,3,2,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp7_el1", CPENC (3,0,3,2,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp7_el12", CPENC (3,5,3,2,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp7_el2", CPENC (3,4,3,2,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp7_el3", CPENC (3,6,3,2,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp8_el1", CPENC (3,0,3,3,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp8_el12", CPENC (3,5,3,3,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp8_el2", CPENC (3,4,3,3,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp8_el3", CPENC (3,6,3,3,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp9_el1", CPENC (3,0,3,3,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp9_el12", CPENC (3,5,3,3,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp9_el2", CPENC (3,4,3,3,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtp9_el3", CPENC (3,6,3,3,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu0_el1", CPENC (3,0,3,4,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu0_el12", CPENC (3,5,3,4,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu0_el2", CPENC (3,4,3,4,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu10_el1", CPENC (3,0,3,5,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu10_el12", CPENC (3,5,3,5,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu10_el2", CPENC (3,4,3,5,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu11_el1", CPENC (3,0,3,5,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu11_el12", CPENC (3,5,3,5,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu11_el2", CPENC (3,4,3,5,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu12_el1", CPENC (3,0,3,5,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu12_el12", CPENC (3,5,3,5,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu12_el2", CPENC (3,4,3,5,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu13_el1", CPENC (3,0,3,5,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu13_el12", CPENC (3,5,3,5,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu13_el2", CPENC (3,4,3,5,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu14_el1", CPENC (3,0,3,5,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu14_el12", CPENC (3,5,3,5,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu14_el2", CPENC (3,4,3,5,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu15_el1", CPENC (3,0,3,5,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu15_el12", CPENC (3,5,3,5,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu15_el2", CPENC (3,4,3,5,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu1_el1", CPENC (3,0,3,4,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu1_el12", CPENC (3,5,3,4,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu1_el2", CPENC (3,4,3,4,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu2_el1", CPENC (3,0,3,4,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu2_el12", CPENC (3,5,3,4,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu2_el2", CPENC (3,4,3,4,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu3_el1", CPENC (3,0,3,4,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu3_el12", CPENC (3,5,3,4,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu3_el2", CPENC (3,4,3,4,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu4_el1", CPENC (3,0,3,4,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu4_el12", CPENC (3,5,3,4,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu4_el2", CPENC (3,4,3,4,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu5_el1", CPENC (3,0,3,4,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu5_el12", CPENC (3,5,3,4,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu5_el2", CPENC (3,4,3,4,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu6_el1", CPENC (3,0,3,4,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu6_el12", CPENC (3,5,3,4,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu6_el2", CPENC (3,4,3,4,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu7_el1", CPENC (3,0,3,4,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu7_el12", CPENC (3,5,3,4,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu7_el2", CPENC (3,4,3,4,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu8_el1", CPENC (3,0,3,5,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu8_el12", CPENC (3,5,3,5,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu8_el2", CPENC (3,4,3,5,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu9_el1", CPENC (3,0,3,5,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu9_el12", CPENC (3,5,3,5,1), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("fgdtu9_el2", CPENC (3,4,3,5,1), 0, AARCH64_FEATURE (POE2))
SYSREG ("fgwte3_el3", CPENC (3,6,1,1,5), 0, AARCH64_FEATURE (V9_4A)) /* FGWTE3 */
SYSREG ("fpcr", CPENC (3,3,4,4,0), 0, AARCH64_NO_FEATURES)
SYSREG ("fpexc32_el2", CPENC (3,4,5,3,0), 0, AARCH64_NO_FEATURES)
SYSREG ("id_pfr1_el1", CPENC (3,0,0,1,1), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("id_pfr2_el1", CPENC (3,0,0,3,4), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("ifsr32_el2", CPENC (3,4,5,0,1), 0, AARCH64_NO_FEATURES)
+ SYSREG ("irtbrp_el1", CPENC (3,0,2,0,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("irtbrp_el12", CPENC (3,5,2,0,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("irtbrp_el2", CPENC (3,4,2,0,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("irtbrp_el3", CPENC (3,6,2,0,5), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("irtbru_el1", CPENC (3,0,2,0,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("irtbru_el12", CPENC (3,5,2,0,4), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("irtbru_el2", CPENC (3,4,2,0,4), 0, AARCH64_FEATURE (POE2))
SYSREG ("isr_el1", CPENC (3,0,12,1,0), F_REG_READ, AARCH64_NO_FEATURES)
+ SYSREG ("ldstt_el1", CPENC (3,0,2,1,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("ldstt_el12", CPENC (3,5,2,1,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("ldstt_el2", CPENC (3,4,2,1,7), 0, AARCH64_FEATURE (POE2))
SYSREG ("lorc_el1", CPENC (3,0,10,4,3), 0, AARCH64_FEATURE (LOR))
SYSREG ("lorea_el1", CPENC (3,0,10,4,1), 0, AARCH64_FEATURE (LOR))
SYSREG ("lorid_el1", CPENC (3,0,10,4,7), F_REG_READ, AARCH64_FEATURE (LOR))
SYSREG ("spsr_svc", CPENC (3,0,4,0,0), F_DEPRECATED, AARCH64_NO_FEATURES)
SYSREG ("spsr_und", CPENC (3,4,4,3,2), 0, AARCH64_NO_FEATURES)
SYSREG ("ssbs", CPENC (3,3,4,2,6), 0, AARCH64_FEATURE (SSBS))
+ SYSREG ("stindex_el1", CPENC (3,0,4,0,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("stindex_el12", CPENC (3,5,4,0,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("stindex_el2", CPENC (3,4,4,0,2), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("stindex_el3", CPENC (3,6,4,0,2), 0, AARCH64_FEATURE (POE2))
SYSREG ("svcr", CPENC (3,3,4,2,2), 0, AARCH64_FEATURE (SME))
SYSREG ("tco", CPENC (3,3,4,2,7), 0, AARCH64_FEATURE (MEMTAG))
SYSREG ("tcr_el1", CPENC (3,0,2,0,2), 0, AARCH64_NO_FEATURES)
SYSREG ("tfsr_el2", CPENC (3,4,5,6,0), 0, AARCH64_FEATURE (MEMTAG))
SYSREG ("tfsr_el3", CPENC (3,6,5,6,0), 0, AARCH64_FEATURE (MEMTAG))
SYSREG ("tfsre0_el1", CPENC (3,0,5,6,1), 0, AARCH64_FEATURE (MEMTAG))
+ SYSREG ("tindex_el0", CPENC (3,3,4,0,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("tindex_el1", CPENC (3,0,4,0,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("tindex_el12", CPENC (3,5,4,0,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("tindex_el2", CPENC (3,4,4,0,3), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("tindex_el3", CPENC (3,6,4,0,3), 0, AARCH64_FEATURE (POE2))
SYSREG ("tpidr2_el0", CPENC (3,3,13,0,5), 0, AARCH64_FEATURE (SME))
+ SYSREG ("tpidr3_el0", CPENC (3,3,13,0,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("tpidr3_el1", CPENC (3,0,13,0,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("tpidr3_el12", CPENC (3,5,13,0,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("tpidr3_el2", CPENC (3,4,13,0,0), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("tpidr3_el3", CPENC (3,6,13,0,0), 0, AARCH64_FEATURE (POE2))
SYSREG ("tpidr_el0", CPENC (3,3,13,0,2), 0, AARCH64_NO_FEATURES)
SYSREG ("tpidr_el1", CPENC (3,0,13,0,4), 0, AARCH64_NO_FEATURES)
SYSREG ("tpidr_el2", CPENC (3,4,13,0,2), 0, AARCH64_NO_FEATURES)
SYSREG ("ttbr1_el1", CPENC (3,0,2,0,1), F_REG_128, AARCH64_NO_FEATURES)
SYSREG ("ttbr1_el12", CPENC (3,5,2,0,1), F_REG_128, AARCH64_NO_FEATURES)
SYSREG ("ttbr1_el2", CPENC (3,4,2,0,1), F_REG_128, AARCH64_FEATURE (V8A))
+ SYSREG ("tttbrp_el1", CPENC (3,0,10,2,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("tttbrp_el12", CPENC (3,5,10,2,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("tttbrp_el2", CPENC (3,4,10,2,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("tttbrp_el3", CPENC (3,6,10,2,7), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("tttbru_el1", CPENC (3,0,10,2,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("tttbru_el12", CPENC (3,5,10,2,6), 0, AARCH64_FEATURE (POE2))
+ SYSREG ("tttbru_el2", CPENC (3,4,10,2,6), 0, AARCH64_FEATURE (POE2))
SYSREG ("uao", CPENC (3,0,4,2,4), 0, AARCH64_FEATURE (V8_1A)) /* UAO */
SYSREG ("vbar_el1", CPENC (3,0,12,0,0), 0, AARCH64_NO_FEATURES)
SYSREG ("vbar_el12", CPENC (3,5,12,0,0), 0, AARCH64_NO_FEATURES)
SYSREG ("vmecid_a_el2", CPENC (3,4,10,9,1), 0, AARCH64_FEATURE (V9_2A)) /* MEC */
SYSREG ("vmecid_p_el2", CPENC (3,4,10,9,0), 0, AARCH64_FEATURE (V9_2A)) /* MEC */
SYSREG ("vmpidr_el2", CPENC (3,4,0,0,5), 0, AARCH64_NO_FEATURES)
+ SYSREG ("vnccr_el2", CPENC (3,4,2,2,1), 0, AARCH64_FEATURE (POE2))
SYSREG ("vncr_el2", CPENC (3,4,2,2,0), 0, AARCH64_FEATURE (V8_3A)) /* NV2 */
SYSREG ("vpidr_el2", CPENC (3,4,0,0,0), 0, AARCH64_NO_FEATURES)
SYSREG ("vsctlr_el2", CPENC (3,4,2,0,0), 0, AARCH64_FEATURE (V8R))
projects / thirdparty / binutils-gdb.git / commitdiff
