reg = <0x20020000 0x1000>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_SLC>;
+ dmas = <&dma 1 1>;
+ dma-names = "rx-tx";
status = "disabled";
};
reg = <0x200a8000 0x11000>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_MLC>;
+ dmas = <&dma 12 1>;
+ dma-names = "rx-tx";
status = "disabled";
};
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk LPC32XX_CLK_DMA>;
clock-names = "apb_pclk";
+ dma-channels = <8>;
+ dma-requests = <16>;
+ lli-bus-interface-ahb1;
+ mem-bus-interface-ahb1;
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
#dma-cells = <2>;
};
compatible = "nxp,lpc3220-spi";
reg = <0x20088000 0x1000>;
clocks = <&clk LPC32XX_CLK_SPI1>;
+ dmas = <&dmamux 11 1 0>;
+ dma-names = "rx-tx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
compatible = "nxp,lpc3220-spi";
reg = <0x20090000 0x1000>;
clocks = <&clk LPC32XX_CLK_SPI2>;
+ dmas = <&dmamux 3 1 0>;
+ dma-names = "rx-tx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
i2s0: i2s@20094000 {
compatible = "nxp,lpc3220-i2s";
reg = <0x20094000 0x1000>;
+ dmas = <&dma 0 1>, <&dma 13 1>;
+ dma-names = "rx", "tx";
status = "disabled";
};
i2s1: i2s@2009c000 {
compatible = "nxp,lpc3220-i2s";
reg = <0x2009c000 0x1000>;
+ dmas = <&dma 2 1>, <&dmamux 10 1 1>;
+ dma-names = "rx", "tx";
status = "disabled";
};
clocks = <&xtal_32k>, <&xtal>;
clock-names = "xtal_32k", "xtal";
};
+
+ dmamux: dma-router@78 {
+ compatible = "nxp,lpc3220-dmamux";
+ reg = <0x78 0x8>;
+ dma-masters = <&dma>;
+ #dma-cells = <3>;
+ };
};
mic: interrupt-controller@40008000 {