arm: [MVE intrinsics] factorize vsrhrq vrshrq

Factorize vsrhrq vrshrq so that they use the same pattern.

2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/iterators.md (MVE_VSHRQ_M_N, MVE_VSHRQ_N): New.
	(mve_insn): Add vrshr, vshr.
	* config/arm/mve.md (mve_vshrq_n_<supf><mode>)
	(mve_vrshrq_n_<supf><mode>): Merge into ...
	(@mve_<mve_insn>q_n_<supf><mode>): ... this.
	(mve_vrshrq_m_n_<supf><mode>, mve_vshrq_m_n_<supf><mode>): Merge
	into ...
	(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 583206dac9e0d2d434cd5b856d10f37f20f38f52..53873704174c4158dce30d830122b374ca2804b6 100644 (file)
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -408,6 +408,16 @@
                     VSUBQ_N_S VSUBQ_N_U
                     ])
 
+(define_int_iterator MVE_VSHRQ_M_N [
+                    VRSHRQ_M_N_S VRSHRQ_M_N_U
+                    VSHRQ_M_N_S VSHRQ_M_N_U
+                    ])
+
+(define_int_iterator MVE_VSHRQ_N [
+                    VRSHRQ_N_S VRSHRQ_N_U
+                    VSHRQ_N_S VSHRQ_N_U
+                    ])
+
 (define_int_iterator MVE_INT_SU_N_BINARY   [
                     VHADDQ_N_S VHADDQ_N_U
                     VHSUBQ_N_S VHSUBQ_N_U
@@ -636,6 +646,8 @@
                 (VRSHRNBQ_N_S "vrshrnb") (VRSHRNBQ_N_U "vrshrnb")
                 (VRSHRNTQ_M_N_S "vrshrnt") (VRSHRNTQ_M_N_U "vrshrnt")
                 (VRSHRNTQ_N_S "vrshrnt") (VRSHRNTQ_N_U "vrshrnt")
+                (VRSHRQ_M_N_S "vrshr") (VRSHRQ_M_N_U "vrshr")
+                (VRSHRQ_N_S "vrshr") (VRSHRQ_N_U "vrshr")
                 (VSHLQ_M_N_S "vshl") (VSHLQ_M_N_U "vshl")
                 (VSHLQ_M_R_S "vshl") (VSHLQ_M_R_U "vshl")
                 (VSHLQ_M_S "vshl") (VSHLQ_M_U "vshl")
@@ -646,6 +658,8 @@
                 (VSHRNBQ_N_S "vshrnb") (VSHRNBQ_N_U "vshrnb")
                 (VSHRNTQ_M_N_S "vshrnt") (VSHRNTQ_M_N_U "vshrnt")
                 (VSHRNTQ_N_S "vshrnt") (VSHRNTQ_N_U "vshrnt")
+                (VSHRQ_M_N_S "vshr") (VSHRQ_M_N_U "vshr")
+                (VSHRQ_N_S "vshr") (VSHRQ_N_U "vshr")
                 (VSUBQ_M_N_S "vsub") (VSUBQ_M_N_U "vsub") (VSUBQ_M_N_F "vsub")
                 (VSUBQ_M_S "vsub") (VSUBQ_M_U "vsub") (VSUBQ_M_F "vsub")
                 (VSUBQ_N_S "vsub") (VSUBQ_N_U "vsub") (VSUBQ_N_F "vsub")

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 20ce7ecb3d6b23af10d45eaa5dd5d47a78a68e35..b5c89fd4105255cbf776b35de74fde7997fb3e79 100644 (file)
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -728,18 +728,19 @@
    (set_attr "length""8")])
 
 ;;
-;; [vshrq_n_s, vshrq_n_u])
+;; [vrshrq_n_s, vrshrq_n_u]
+;; [vshrq_n_s, vshrq_n_u]
 ;;
 ;; Version that takes an immediate as operand 2.
-(define_insn "mve_vshrq_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_n_<supf><mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
        (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
                       (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
-        VSHRQ_N))
+        MVE_VSHRQ_N))
   ]
   "TARGET_HAVE_MVE"
-  "vshr.<supf><V_sz_elem>\t%q0, %q1, %2"
+  "<mve_insn>.<supf><V_sz_elem>\t%q0, %q1, %2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1401,21 +1402,6 @@
   [(set_attr "type" "mve_move")
 ])
 
-;;
-;; [vrshrq_n_s, vrshrq_n_u])
-;;
-(define_insn "mve_vrshrq_n_<supf><mode>"
-  [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
-       (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
-                      (match_operand:SI 2 "<MVE_pred2>" "<MVE_constraint2>")]
-        VRSHRQ_N))
-  ]
-  "TARGET_HAVE_MVE"
-  "vrshr.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
-  [(set_attr "type" "mve_move")
-])
-
 ;;
 ;; [vabdq_f]
 ;;
@@ -4661,35 +4647,19 @@
 
 ;;
 ;; [vrshrq_m_n_s, vrshrq_m_n_u])
-;;
-(define_insn "mve_vrshrq_m_n_<supf><mode>"
-  [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
-       (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
-                      (match_operand:MVE_2 2 "s_register_operand" "w")
-                      (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
-                      (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
-        VRSHRQ_M_N))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vrshrt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
-;;
 ;; [vshrq_m_n_s, vshrq_m_n_u])
 ;;
-(define_insn "mve_vshrq_m_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
        (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
                       (match_operand:MVE_2 2 "s_register_operand" "w")
                       (match_operand:SI 3 "<MVE_pred2>" "<MVE_constraint2>")
                       (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
-        VSHRQ_M_N))
+        MVE_VSHRQ_M_N))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vshrt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
+  "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])