RISC-V: Fix asm check for Vector SAT_* due to middle-end change

The middle-end change makes the effect on the layout of the assembly
for vector SAT_*.  This patch would like to fix it and make it robust.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Adjust
	asm check and make it robust.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c
index 348313b511f472323cd73b80ff1f605ddb957441..d7d1dae010d55b3477cc7394191fa25d6d14b1e1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c
index 425d4c768d6a270bf5f63877106beeefb7014f0e..4397c10943a57cb3e3fe42fd8ffe58e3cd7b7a86 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c
index 903ae36e464f7944f11a14bf17d15dde4df0ab66..b93b582680f208a962ce48f5a05a630f726620fa 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c
index b9db496f2fa87bb6291a7a1e4e17163a80d021a0..ec3c6af4ee6529de6bb6210a9ca48aae1b7b56e1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
index 72d17c0a971e8e876b1606b63ff483ebd0aa6607..35f17c1b82d4a9859e37dec102536b321158711f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c
index 1aa4fbe701fc20e457acf4922cb5a55845b60178..116908431604c8ee949bc45d9b3e25e35ea46a05 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
index 664fa61d67c700b865f4cd8313846a12250e5c89..9949047a6c7fc1c47e5a7eb560f25b1b6c339528 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c
index f752327e95173658a13d6589dcdc5e595627b0bf..84c44f9a46bba227d859f2006d26361a4d76db52 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c
index 352e22e56e5cdea58d79e9df0303acc9445cd9a1..5f61acbec0d13d2394737d883c9a0b6bf1ca551f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c
index 7a1996d38bc71b40800a9644cdcd68b612324081..eb4486ca765bdd40bf27cf2d39308e891cae625e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c
index c01c9f468a4abbb7754268efbf2dbf31c6ebfa2a..470eb6b3cfec59a3dd134168e54954f539cf48c7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c
index e4f7c64331b4990c81b6d8ca42526f9474613cd9..b381c05091abed90601b72e3a7c077ae247f274a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c
index 66ca4cd2749f61e461c731dd68bb274c1815aff0..6bd2c30c13973ebd420c942b99c353a4860c5984 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
index 2e77b067cf371e1f93aa85854bef533f74d17c13..c525ba97c5298311319bc5d91411509d78b5cb7c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
index 2e824049874b75b794d01489133de711b7508e37..41372d08e52d8bd8e629002d7f828ae1ecb3f53e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c
index 9283ce340b86c66bd960faa271b57e7adb6f11f7..dddebb54426fa5b1485d5766c0845304ba05201d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c
index fcf7c9281400acc3f3a4e3f354e5a008add1c911..ad5162d10a03ac56ed5d2854d8c2d44ce5c9c62a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c
index a5ca9228a20ff45bfae35c10a18ce0aa9062beac..39c20b3cea643476788180ddad3e23f8647fdc2d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c
index 9d379ae46a121c32fe41a027ac1c77d4518b7b10..6eefaeebf318a58e816cd3b62ca575c21aa6dfc4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c
index 7b89fe1c3cfb3c63601020a2338c289ad67d3436..78beb1bd39e2cc4678cdfb8de027f42d8e72f71f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c
index f7c37df2888529e45a952be7ec0613f9b86e6944..369fa296d08faa4d2d7a3fbe0c5fe4a3abe7cfd3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
index fbf57ff164217bd87b9f36f3022be51cd7a69a7a..e827cdd16570535221613c37806eee89c8863ee4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c
index a0847c90f3f5f1be05e958ef1dd27828857042e8..97a9b1fb9732d5083c38b05289618dbe1cde4edf 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c
index e8b6de3ceb387d743126d6e7fb6ea4a6e930e76e..af16f48e228a090de85c06bc5a96b73fc3eb4a8b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c
index 57f4bf2c4275a31b92208c7ac045b98e031fa585..0a8eabfbad1b93a9377364bdb6d7e240863a87ae 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c
index 47a3bc1c2f2860278440512e0e31f06f059cf49e..38cbdfbcf0755e3e8f253f04fdb25f5a39a9d94f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c
index 3556761c430b86d6327751fc7941cfb066e4aed8..8da2cb413d80a1de7f7cd07ea10d626d4ce94d9c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
index c89ecea75cc62de16d8735963b9d276edc69a5bd..fe8a5a8262d5b7afbc16e3f8854fc68fb6b6a066 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c
index 0f0f4542fb2e215ba903951a02f7906b5b09abdf..1aeb24eed0d5693f38935682cdbc84777404952a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c
index e0e311d8b5b90e56ee76173f5e1e94d86d468acf..0d2b0e4ab809b46f381376d4e0efbd23cbe52210 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c
index b76b231c06ee8135cf0f04dd73ffef22c4e2314a..168c269f75e881401add1ecb52c76cabc144a72f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c
index b13ff0aad8b0163a8574a115cb4681f67fb0f64b..d636302842cbd0b26fdab45729512793033ad126 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c
index f0ce17d19591193e13de83dba3752d8c80147411..5d21430172737b36084e005b7b5e1ba48fcbb991 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
index fac941945e9e3cc5ba37163a54e22df658832f91..e50121bd0319bb4374cef3401820782dada18a1e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c
index 0c6afc391b41ef2f2fcd8daeb73d8e98b461d1a1..de460c176a2f21c7e22352731a876612ede9f771 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c
index 41fe3b86deb1b2e1c72f16ad691373cd9a35a49e..96e06f0c6be2a5939483eebcfe6b13112010a649 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
index a52e38a7ed28f3963232abb99beba830fe2ff510..dffe957629a371de660ecf61470b4de263f35943 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c
index 1ee8391d8838b3facac9407485d35573a1149410..97b2e17e74aa1871bc3eb96e7a985e292925f285 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c
index d74a98224318b51e71b5a5b7e83f632b550cbb24..978c37ca1384ff52f4dc75275151e4a45f400c79 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c
index 70284382fba0e5e32f44577df3bf21b7120c530a..f43c5711ecaf973e13d8221a3c400f18e9e19f20 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
index d44514cdb97405540eff3d10a4e0b4ca64c391c4..f435b6e08311d4a6f7ccaa9b1c98479fd20b579a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c
index 5dbbf202b1f3afa1b82182e30979f1aae02099aa..74fe1e31804e3a35d1c0fb1d67d2100d15c0f846 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c
index 4696753b903cdd3064aa67396cbeb28f959de5cd..b83b87b2b1bf84128553f96e2f44967f84e216d1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c
index c73413a4597ab376b9594d96dd1b21d9b28150a7..549970684fab9fdc0032582e40c5cbe1f25585f1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c
index b963ba1e1e1c2de708c2a07143ca2e933923ead3..0ae3c37a7834958c04d18e634c2304d3b4a98ae9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
index fc2682bd24f258d30e4acef1883fbc87a32cf9ad..e16a0d22cbbeb8318d9714920451e803362606f8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
index 4e51e4aa7f821a769a7814c3e656aef91e9d628c..6b4bc69c005d1be4e489b8bf94ec6347cfb26160 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
index b16925ebac36329b2604839896e590b89c41aab1..6be7c7669dea179c0d93bc677edeb3cad2f40139 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
index 9d99a4ea71cd30d624de22528c7f9b2744f955be..e9eb157fb9d14fd63a284465fa53506aa9372c85 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
index 424551e1500655d8507d86fe01d26a1690ac31b6..4980789dcd48e0698794ac845407e6914d064528 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c
index 110318824d86d09173bc9e33593f3d4af9cfb4c4..2a4d1cc93e7f7a43b5f1718541cac95242715925 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c
index 981c0713c18ca7da342ca578452e6856beb38628..8c14d9a2c01ef638bc09ae5aa7a65c0197fae9c0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c
index 159153727132f61dd816bd6dff12ac618e74304a..32d3a62d30389908b186eff33bd1a3537f47bb1d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
index 9c971f6a3d1ec8c555349f6f3e2b9d50dd8365a0..8c098ac336a546853ab4792e3cb06226c7a80a48 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c
index 447b6814b8abdcd3da864b607c97bddb5086bda2..2af04851e04abd8ed4d7f95801d9fc4c2d39a4af 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c
index 09bcd0d34689f626b8c4541a8216a04365c66b01..4a4fc746326612465a0e728f1023e4c1143f0020 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c
index 704f560b79ad9c1795e8e866a516c4e882cb7be7..5c912a32549b7571f749d67271d93308cb338ca8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c
index 8011f6c19ccfda2b3bfa6de0ba0aafcd0bff08fd..50aa0ae59d7a1dcd3b49ef692f30c14c4f73b456 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c
index 2a5727677eddf84241c8f31ef1b00fda28a0bceb..329dd230b02fa37827fc26be47ed2237e0b26098 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_9:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c
index 4a7d7e55c9f495f243621ac93bbf317c4bbe546e..a024eadc2a75281dd9a034c10b775ab6396a4a30 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_9:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c
index cfad5d787e374f62534643b5150ebc21729c2f52..56216e976206d46200143dc3775a1a9253018c09 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_9:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c
index 721fd27a28898ad302ac73cf4cd6d5bd38a11a93..707bfd2e1c695f5ebfba6b3bce94f4d3054b7334 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_9:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
index 1e3b5e7bf3e947c0a6b978287ccbe859470530ae..e7dc212fe520dd2792f01ef0218a02334e11b18d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_10:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c
index 4bc3205dc3085c3d8e795a5f484ba6cd2cb3b950..b814830da32bfc52a1d39a5a626457e7f2a4d3f1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_10:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c
index 3ec28cd3fc74fe50063d8265ee7c94fc0e905013..e6c6aaac800d59a21336de5b821f88c2c737e3a0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_10:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c
index 5eca3debeaf23a17e16fce4353cd5066c1eef2b3..21727fb3a43e2a9a5bd3056f3280930b10aee03c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c
index 656c35cc22a13d7baf97ce87743282394865e27d..716e58e8ae3959d51c9efa259204b789125218b0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_10:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c
index 942d2e91acc1167ad23eee98fc97e63322da9609..e1d78aff28c26429754972c3918f7570b9d14825 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c
index c27fc4d53312fca27f1e6eed9c5b09f6c8b43473..9911cbcfb3787b11bd1009dc2382a5e5a562194c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c
index 817435955a5fa13b0cab94069852b965dc37bf06..8c83af1fc674f78699957a66900c7f6c5ca14581 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c
index 42cf16f13b069ac6df30ff25cc81628d3fd6f04f..d76d754b72183110146aa2c848568cb4331db549 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c
index 9eb26d9f52c5e5c36801df0a2a89e058521e6cf0..3b6b53274f2bf518ab6ceb2a35935c9ae647e36d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
index ab2287032d6b4596a8051c4bb25d31be82e50132..792d8a028772b7ff6bc3fda344d8f0c92506c3f5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
@@ -8,11 +8,12 @@
 /*
 ** vec_sat_u_sub_trunc_uint8_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** ...
 ** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
index 2c752e7225866a2eb6136dd267e83b0f0fdbdb3c..67780360ce1ea869e92f68d4fc38a802f309ff3e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
@@ -8,11 +8,12 @@
 /*
 ** vec_sat_u_sub_trunc_uint16_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
index 7f89d7099b07118dedf964e62cbe892bf5da572e..04f2d0b2d95c791ea41568431dcfabc7ab24e76f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
@@ -8,11 +8,12 @@
 /*
 ** vec_sat_u_sub_trunc_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
 ** ...
 */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
index ae3e44cd57e80b8a6aee741ba343c21b5bc3f3fa..60ab5382fa9bbbaef285b7ec7223d5d3deeaf95d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint16_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
index f5084e503ebd5cafc7fdfd2fa623b37127a23ac3..2566450445f10f3395360f6771de1681768cd5ee 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint32_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
index e2ab880a1acaceb4aa2285818c528e140c80fc9d..f90432bb9031e4d5de319c4c6d4d5ac922836f08 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint64_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c
index e996c9442dd7b3fcc690a41a7b32c36e65d53f95..5330e19c6792604773eb556cd2bc070a44fb29f6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint32_t, uint64_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
index 49bdbdc36062642ef0ea1e5292a3c9c69922e041..45d74eab2cdb9d6a9435df44560d2d157fd56269 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint16_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
index 3ff696edcfee87d70a4bfbca351d1fb60b5cb6fb..c9ce878827456e3973620a349f207610bce257b8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint32_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c
index 7fca4a43fd3089dd157761cb59216c134046b815..5529c710f921b81c87814025e61a5ab54e4d8108 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c
@@ -8,14 +8,17 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint64_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c
index 201fcaa4f6945d4e104afda9d681de81c9f17be5..6d773e96da39c1837e1ffa540257073e5ae8eb7c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint16_t, uint32_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c
index 99a9600102c6fb242b2dc8094e2aceee01dba7a3..808f62bff10f0391cfbade25609dcec934fc8db3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint16_t, uint64_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c
index f1bd5400f6b444481bdd2ce353b4f24ff10f38ae..12a0e2ff38014baa58861bebe82a4c14222665d4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint32_t, uint64_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
index a80cefe46ab083b2189012ad1878a35d2be4a84b..9c7979d326cd3d9561495fa3a9687e60f1469775 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint16_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c
index 2516468fd167e4c02c74b976a98836382cc86ffc..cf6f404f65ef42408d3d1f26b49e57701699cae8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint32_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
index 9a4d261d052d03d3143e7a9434661f6f33d41380..2e497b7ec1c52cc7a67052fed92a6f6ddd514fbc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint32_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c
index 5f0b71be8349e1ed75e46ef69d423e7352cb148d..dd996d21c5ecf8819ec48c54a8cc22b34c571b5d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c
@@ -8,14 +8,17 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint64_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c
index 059758b8bb3dbb1adc9cd9dd0ad6cca1911cacd4..a6c125408ce9ba48757b0b34d5f5efc1bd718b44 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint32_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c
index 6e094d071119c9bbbf54254d5b47a15d048d2162..2551b2f5a0572943939c95da5b9b820f8427f997 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint64_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c
index 707b20b0e01a758034a261c1cbbc265388a3d980..bfcfa805e19eea9b8560ee06b6be5f082418cc50 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint32_t, uint64_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c
index 5df05f72cbb568582e11e428fd4ddfc22acb216c..787c5644bb087ca8391b1a44737c9ecd36ff077a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c
@@ -8,14 +8,17 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint64_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c
index 89dd65374a55cae5c6aa97a9ebeb1045df24ab2c..b236c2a2caf28b665d3f8b31139d431324637fab 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint16_t, uint32_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c
index 851a20e5037b065f7673dc2fa52b8c06a349eafd..1747585c59e40365cfe7a669b81c284e59096de6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint16_t, uint64_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c
index 8ae3bc243cd3e7cbb432049ff5d8bae517d13e93..fd30184b1de4bfe817220b8be5d13c11d1a9207e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint32_t, uint64_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c
index a5b566b6d80ea321f360c2efc26490d6ba157afa..dc9bbb5fe96d8a4542f8c2330902278012a12f62 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint16_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c
index a6df321057ee7dadbbad2176535ee78f1ef88f2a..0525b8f5159bf078570c1dbaadaaae01b6efcc61 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint32_t)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c
index 7c68825213f49c9488e50a1ecddb866aff86011f..96621231999f272efff761f1ebfefcec35e5d659 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c
@@ -8,14 +8,17 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint64_t)